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DatePosted 21 Days Ago
ASIC Physical Design CAD, Timing Constraint and Analysis
ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will......
Hiring In China, Shanghai
full-time Sourced PhD 2-years NVIDIA China
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