As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on micro-architec......
More Than 30 Days Ago
Senior ASIC Physical Design Engineer, Cache Coherent Interconnects 
full-time
Sourced
OND
5-years
