Physical Design Engineer job opportunity at Celestial AI.

Home Jobs In United States Of America Tag: Design Engineer Physical Design Engineer position at Celestial AI


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Celestial AI Physical Design Engineer
Experience: 5+years
Pattern: On Site
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Design Engineer

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degreeBachelor's (B.Eng.)
loacation Santa Clara, California, United States Of America
loacation Santa Clara, C..........United States Of America

As #Generative #AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions. The #Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies. This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers. __ Develop and implement high-performance, low-power, area efficient physical design for SOC and block level #designs using industry standard EDA tools. __ Work closely with digital and analog design teams to understand design requirements and constraints to be able to implement physical design. __ Contribute to physical #design flow #development. __ Resolve or find workarounds for tool issues, independently or working with EDA tool vendors. __ Work closely with #synthesis team to help provide feedback on design feasibility, constraints, timing, power, placement and routing issues. __ Perform physical verification, STA, EM & IR Drop #analysis.

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