AI Security Architect, Principal job opportunity at d-Matrix.



bot
d-Matrix AI Security Architect, Principal
Experience: General
Pattern: full-time
apply Apply Now
Salary:
Status:

R&D - CTO & Architecture

Copy Link Report
degreeBachelor's (B.Sc.)
loacation Santa Clara, United States Of America
loacation Santa Clara....United States Of America

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid (Santa Clara, CA) or Remote The role: AI Security Architect (Principal) d-Matrix is seeking an outstanding security architect to help integrate solid secure computing principles into our high performance AI accelerator systems that meet or exceed the needs of our datacenter customers. Taking a wholistic view of security, we incorporate security features from silicon to the upper levels of the stack to enable customers workloads to execute in a reliable and safe environment irrespective of the deployment scale. What you will do: As a member of the architecture team, you will contribute to hardware and software security features that enhance the next generation of our inference accelerators This role requires to keep up the latest research in ML, architecture, and security domains, and collaborate with different partner teams including design, verification, and software You will help assimilate customers’ security requirements to define the threat model and mitigation features for our computing systems, subsequently working with the engineering teams to incorporate them at the appropriate design levels What you will bring: Minimum: MSEE with 15+ years of experience or PhD with 10+ years of applicable experience Solid grasp through academic or industry experience in multiple of the relevant areas – computer architecture, secure computing, distributed systems, datacenter reliability/manageability, ML fundamentals Hands-on experience with authentication, isolation, encryption, device signing, servicing in datacenters, and HW-SW feature definition of the same Programming fluency in C/C++ or Python, ability to learn new concepts and quickly prototype for experimentation Research background with publication record in top-tier architecture, security, or machine learning venues is highly desired Self-motivated team player with strong sense of collaboration and initiative Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Other Ai Matches

Micro-Architect / RTL Design - CPU, Principal Applicants are expected to have a solid experience in handling R&D - HW Silicon Design related tasks
AI / ML System Software Engineer, Senior Staff Applicants are expected to have a solid experience in handling R&D - SW Kernels & Workloads related tasks
Analog Design Engineer, Senior Staff Applicants are expected to have a solid experience in handling R&D - HW Analog Circuits related tasks
Analog IC Design Intern Applicants are expected to have a solid experience in handling R&D - HW Analog Circuits related tasks
Design Verification Engineer, Senior Staff Applicants are expected to have a solid experience in handling R&D - HW Verification related tasks
FPGA Design Engineer, Senior Staff Applicants are expected to have a solid experience in handling R&D - HW Silicon Design related tasks
Compiler Architect Applicants are expected to have a solid experience in handling R&D - CTO & Architecture related tasks
Analog Design Engineer, Staff Applicants are expected to have a solid experience in handling R&D - HW Analog Circuits related tasks
Machine Learning Intern - Dynamic KV-Cache Modeling for Efficient LLM Inference Applicants are expected to have a solid experience in handling R&D - SW Kernels & Workloads related tasks
Director, Partner and Supplier Management – AI Hardware Applicants are expected to have a solid experience in handling R&D - Operations & Supply Chain related tasks
HW Engineering Intern - PCB Layout Automation & AI Tooling Applicants are expected to have a solid experience in handling R&D - HW Systems Engineering related tasks
AI Software Applications Engineer Applicants are expected to have a solid experience in handling S&M - Product related tasks
AI Security Architect, Principal Applicants are expected to have a solid experience in handling R&D - CTO & Architecture related tasks
Machine Learning Research Intern Applicants are expected to have a solid experience in handling R&D - SW Machine Learning related tasks
Technical Recruiter, Senior Staff Applicants are expected to have a solid experience in handling G&A - Recruiting related tasks
Digital Design Engineer, Micro-Architect, Principal Applicants are expected to have a solid experience in handling R&D - HW Silicon Design related tasks
Design Validation Engineering Intern Applicants are expected to have a solid experience in handling R&D - HW Validation related tasks
Design Verification Engineer, Staff Applicants are expected to have a solid experience in handling R&D - HW Verification related tasks
Application Performance Engineer Applicants are expected to have a solid experience in handling S&M - Product related tasks
HW Systems Engineer, Customer Platforms - Tech Lead/Principal Applicants are expected to have a solid experience in handling S&M - Product related tasks