Lead FPGA Design Engineer job opportunity at Astrome Technologies Pvt. Ltd..

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Date2025-01-20T17:34:53.000Z bot
Astrome Technologies Pvt. Ltd. Lead FPGA Design Engineer
Experience: 8-years
Pattern: Full-time
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loacation Bengaluru, India
loacation Bengaluru....India

Job Description Astrome Technologies is at the forefront of developing innovative 5G ready wireless systems that fulfill high bandwidth networking requirements in both rural and urban settings. We are seeking a dynamic and experienced Lead RTL Design Engineer to guide the development of our wireless baseband architecture. Lead the definition and implementation of RTL architectures and participate in the specification and design of complex communication systems. Oversee and mentor a team of engineers in the design, verification, and implementation of RTL designs using System Verilog. Conduct synthesis, implement designs on FPGAs, and resolve timing violations. Collaborate with Software and Hardware teams to troubleshoot and optimize system performance issues. Ensure adherence to design methodologies and best practices throughout the development process. Required Skills: 8+ years of experience in RTL design and verification, with a proven track record in leading design teams. In-depth expertise in digital design principles, RTL design, and FPGA development flows. Advanced proficiency in HDLs, particularly SystemVerilog/Verilog for RTL Design. Strong experience in designing IPs using AXI4, AXI4 Lite, and AXI4 Stream Protocols. Comprehensive understanding of Xilinx FPGA architectures and proficiency in using tools like Vivado. Solid knowledge of digital signal processing techniques, including Fast Fourier Transform, linear algebra, and complex algebra. Experience in the realization of baseband processing for wireless systems, such as OFDM. Proven ability to innovate and research unfamiliar technologies applicable to product development. Strong organizational skills with the ability to manage projects, timelines, and cross-functional communication effectively.

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