Staff Engineer, Static Timing Analysis job opportunity at Samsung.

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DateMore Than 30 Days Ago bot
Samsung Staff Engineer, Static Timing Analysis
Experience: 6-years
Pattern: full-time
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Static Timing Analysis

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loacation 3900 N Capital of Texas Hwy, Austin, TX, USA, United States Of America
loacation 3900 N Capital..........United States Of America

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities As a Staff Static Timing Analysis (STA) Engineer, you will work on ensuring timing integrity and signoff readiness for Samsung’s next-generation GPU IPs used in premium smartphones and adjacent market segments.   In this mid-level individual contributor role, you will collaborate closely with RTL, physical design, SoC integration, and EDA partners to develop and implement timing analysis and convergent strategies for complex GPU designs. You bring curiosity, hands-on STA expertise, a solid understanding of ASIC design flows, and a collaborative mindset to apply sound methodology and deliver high-quality timing closure across functional and test modes. You execute hands-on static timing analysis at top level, developing, debugging, and maintaining timing constraints, clock definitions, and timing environments for complex, multi-clock GPU IPs across functional and test scenarios. You support timing closure and signoff readiness by analyzing timing paths, understanding different clocking and implementation styles, managing latency and skew tradeoffs, and applying timing budgeting, derating, and multi-voltage methodologies across advanced process nodes. You help advancing cross-functional collaboration with RTL, physical design, and SoC teams to identify, debug, and resolve timing issues impacting block-level and full-chip closure, ensuring alignment between logical intent and physical implementation. You contribute to technical excellence by applying and help influencing STA methodologies and sign-off flows, leveraging industry-standard tools and exploring best practices—including POCV, multi-corner analysis, and low-power constraints—to improve timing quality, convergence, and predictability. You take initiatives on moderate-to-complex projects, communicating openly, documenting analysis and results, demonstrating strong ownership and continuous learning mindset by staying ahead of emerging GPU technologies. Skills and Qualifications 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a Ph.D. Solid understanding and hands-on experience with ASIC design flows and electrical engineering fundamentals. Working knowledge and experience with POCV, derating methodologies, and timing analysis. Strong hands-on experience with industry-standard STA tools ( e.g. PrimeTime, Tempus). Solid hands-on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs. Working knowledge of formal equivalency checks, low-power checks, timing constraints, UPF. Strong scripting /programming skills in Tcl, Perl, Shell, and/or Python. Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach. Excellent written and verbal communication skills for documenting designs, methodologies, and best practices. Excellent collaboration skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global team environment. Nice to have: Familiarity with advanced FinFET process nodes (5nm or smaller). Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools. Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure. Our Team The Advanced Design Technology and Design Implementation teams play a critical role in driving technology development across Samsung System LSI business. Operating at the intersection of design technology and physical implementation, we engage with Foundry partners from early-phase technology exploration through the full design lifecycle. Our teams span advanced design process and methodology development, GPU physical design and implementation, CAD, and DTCO—accelerating adoption of advanced technology nodes and enabling market-differentiating power, performance, and area (PPA), silicon reliability, and design turnaround time for GPU and system-level IP solutions. You will join a diverse, highly collaborative organization working across concurrent-development cycles, with direct impact on consumer technologies used worldwide. Here you’ll help build what’s next, experiment with new ideas and explore different GPU development verticals, broaden technical expertise, and solve impactful challenges in a supportive environment that values collaboration, continuous learning, and growth. Total Rewards At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,000 and $226,600. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance. Additionally, this role might be eligible to participate in long term incentive plan and relocation. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA). U.S. Export Control This position requires the ability to access information subject to U.S. export control restrictions.  Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information. Trade Secrets By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity. #SARC * Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here . * Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and  provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

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