Senior Mask Designer job opportunity at NVIDIA.

Home Jobs In India Tag: Job Senior Mask Designer position at NVIDIA


DateMore Than 30 Days Ago bot
NVIDIA Senior Mask Designer
Experience: General
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeGeneral
loacation India, Bengaluru, India
loacation India, Bengalu..........India

We are looking for a Senior Digital/Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! What you'll be doing: Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies. Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes. Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows. Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks. Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies. Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts. Possess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions. Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability. Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives. Excel in resource management, representing the team in technical discussions with customers What we need to see: B.E/B Tech. / M Tech in Electronics or equivalent experience with 8+ Years of proven experience in Memory layout in advanced CMOS process. Detailed knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance memories of various types. Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding) Experience with floor planning, block level routing and macro level assembly. Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status #LI-Hybrid

Other Ai Matches

Senior Production Planner Applicants are expected to have a solid experience in handling Job related tasks
Senior NPI Infrastructures Engineer Applicants are expected to have a solid experience in handling Job related tasks
Hardware Application Engineer – High-Speed IO and Memory Applicants are expected to have a solid experience in handling Job related tasks
Senior Storage and Networking Product Engineer Applicants are expected to have a solid experience in handling Job related tasks
Solutions Architect, AI and ML Applicants are expected to have a solid experience in handling AI and ML related tasks
Senior Architect, GPU Profiling System Applicants are expected to have a solid experience in handling GPU Profiling System related tasks
Senior Research Engineer, Foundation Model Training Infrastructure Applicants are expected to have a solid experience in handling Foundation Model Training Infrastructure related tasks
Senior Software Engineer - VLM Microservices for Neural Reconstruction Applicants are expected to have a solid experience in handling Job related tasks
Software Engineering Manager, Robotics 3D Perception and Simulation Applicants are expected to have a solid experience in handling Robotics 3D Perception and Simulation related tasks
HR Specialist - New College Grad 2026 Applicants are expected to have a solid experience in handling Job related tasks
Senior VLSI Library Methodology Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Software Test Developer - Robotics Applicants are expected to have a solid experience in handling Job related tasks
Enterprise Account Manager, Robotics Applicants are expected to have a solid experience in handling Robotics related tasks
NVIDIA 2026 Internships: Computer Architecture - US Applicants are expected to have a solid experience in handling Job related tasks
remote-jobserver Remote
Senior ASIC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
SoC Power Architect Applicants are expected to have a solid experience in handling Job related tasks
Manager, Developer Technology Enterprise AI Applicants are expected to have a solid experience in handling Developer Technology Enterprise AI related tasks
Senior Deep Learning Performance Architect Applicants are expected to have a solid experience in handling Job related tasks
Senior Datacenter Resiliency Architect Applicants are expected to have a solid experience in handling Job related tasks
Principal Data Platform Architect Applicants are expected to have a solid experience in handling Job related tasks
System Software Engineer - Autonomous Vehicles Applicants are expected to have a solid experience in handling Job related tasks
Digital Circuit Design Intern - 2026 Applicants are expected to have a solid experience in handling Job related tasks
System Products Memory Solutions Engineer Applicants are expected to have a solid experience in handling Job related tasks