ASIC Physical Design CAD, Timing Constraint and Analysis job opportunity at NVIDIA.

Home Jobs In China Tag: Timing Constraint and Analysis ASIC Physical Design CAD, Timing Constraint and Analysis position at NVIDIA


DatePosted 19 Days Ago bot
NVIDIA ASIC Physical Design CAD, Timing Constraint and Analysis
Experience: 2-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Timing Constraint and Analysis

Copy Link Report
degreePhD
loacation China, Shanghai, China
loacation China, Shangha..........China

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world. What You’ll Be Doing Develop timing analysis and timing closure methodologies, and implement flow automation for large-scale, high-speed semicustom chips based on deep submicron processes. Establish methodologies for timing constraints and SDC (Synopsys Design Constraints) release, including automatic constraint generation, constraint linting, and validation of timing exceptions. Take responsibility for EDA tool evaluation, and collaborate with EDA vendors to enhance commercial timing signoff tools and constraint lint tools. What We Need To See  Master’s or PhD degree in Electrical Engineering or Computer Engineering, with 2+ years of hands-on experience in physical design implementation or RTL simulation. Proven experience in synthesis, timing constraints definition, timing analysis, and timing closure. Advanced proficiency in commercial STA (Static Timing Analysis) tools, such as Synopsys PrimeTime, Cadence Tempus, Synopsys TCM, or Ausdia TimeVision. Solid expertise in STA principles and timing signoff processes. Proficiency in at least one programming/scripting language, including Perl, TCL, Python, or C++. Strong verbal and written communication skills, with the ability to collaborate effectively in cross-functional teams. Ways To Stand Out From The Crowd Experience in flow development or automation for ASIC backend design. Knowledge and experience in RTL simulation and validation.

Other Ai Matches

Senior Deep Learning Engineer - Model Evaluation & AI Systems Applicants are expected to have a solid experience in handling Job related tasks
Senior Software Engineer - Networking Applicants are expected to have a solid experience in handling Job related tasks
Manufacturing Test Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Memory System Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Automotive Sensor Ecosystem Engineer - Autonomous Vehicles Applicants are expected to have a solid experience in handling Job related tasks
Senior System Software Engineer - Data Engineering Applicants are expected to have a solid experience in handling Job related tasks
Global Head of Business Development, Digital Health Applicants are expected to have a solid experience in handling Digital Health related tasks
Firmware Manager - NVLink Applicants are expected to have a solid experience in handling Job related tasks
Senior Lab Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Solution Architect, HPC - NVIS Applicants are expected to have a solid experience in handling HPC - NVIS related tasks
ASIC Physical Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Deep Learning Performance Architect Applicants are expected to have a solid experience in handling Job related tasks
Senior CAD Engineer - DFX Software Applicants are expected to have a solid experience in handling Job related tasks
Senior Software Test Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior SRAM Co-Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior HPC and AI Networking Performance Research and Analysis Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior GenAI Technical Lead, Partner Platforms Applicants are expected to have a solid experience in handling Partner Platforms related tasks
Global Commodity Manager, Semiconductors Applicants are expected to have a solid experience in handling Semiconductors related tasks
Senior Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
remote-jobserver Remote
Senior Software Architect - Deep Learning and HPC Communications Applicants are expected to have a solid experience in handling Job related tasks
Senior Counsel, Product Legal – Software Applicants are expected to have a solid experience in handling Product Legal – Software related tasks
Senior Manufacturing Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Software QA Automation Infrastructure Engineer Applicants are expected to have a solid experience in handling Job related tasks