Electronic Design Automation Intern - 2026 job opportunity at NVIDIA.

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DatePosted 16 Days Ago bot
NVIDIA Electronic Design Automation Intern - 2026
Experience: General
Pattern: full-time
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degreePhD
loacation Taiwan, Hsinchu, Taiwan
loacation Taiwan, Hsinch..........Taiwan

NVIDIA's success builds on a foundation of industry leading hardware. We achieve distinction through extensive design optimization, including combining the best of external EDA with highly optimized, internal EDA tools. Our team develops these tools by fusing advances in parallel computing, machine learning, and specialized algorithms for VLSI design. We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.). Understanding both software and hardware aspects is the key. Creativity and self-drive to explore and perfect fast, high-capacity software is required. If you like to work across many technical areas and see your successes directly realized in the world's best AI hardware, it does not get any better than this! What you’ll be doing: Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools. These tools already outperform the industry's alternatives in high capacity timing closure and will advance even further with your contributions. Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction. As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment. What we need to see: Pursuing BS, MS, PhD or equivalent experience in Electrical Engineering or Computer Science Solid experience in VLSI algorithms development using C++. Strong programing skills. Strong communication and interpersonal skills Ways to stand out from the crowd: Familiarity with C++14 or newer experience, such as lambdas and concurrency, as well as design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python. Detailed understanding of how multiple Physical Design steps interact and how they can potentially be fused together to form hybrid engines that result in better PPA, and VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc. Experience in high performance software design including CUDA programing, multithreading, distributed computing, efficient memory and I/O use, etc., and highly driven to craft outstanding software towards improving PPA with a dedication to continuous improvement. Background with reinforcement learning, GNNs (Graph Neural Networks), and other relevant machine learning frameworks, especially as applied to physical design. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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