Memory Mask Design Engineer job opportunity at NVIDIA.

Home Jobs In India Tag: Job Memory Mask Design Engineer position at NVIDIA


DatePosted 5 Days Ago bot
NVIDIA Memory Mask Design Engineer
Experience: General
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeGeneral
loacation India, Bengaluru, India
loacation India, Bengalu..........India

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for a Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. What you'll be doing: Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies. Deliver layouts for Full Custom Memory group specializing in digital Memory circuits. IP layout will comprise of significant digital components. Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts Follow company procedures and practices for IC layout activities. What we need to see: B.E/B Tech. / M Tech in Electronics or equivalent experience with 2+ Years of proven experience in Memory layout in advanced CMOS process. Detailed knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance memories of various types. Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding) Experience with floor planning, block level routing and macro level assembly. Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

Other Ai Matches

ASIC Physical Design and Timing Engineer - New College Grad 2026 Applicants are expected to have a solid experience in handling Job related tasks
Senior Software Engineer, Deep Learning Inference Applicants are expected to have a solid experience in handling Deep Learning Inference related tasks
Research Engineer Neural Reconstruction - New College Graduate Applicants are expected to have a solid experience in handling Job related tasks
Senior Software Engineer, Soc DPU Platform Applicants are expected to have a solid experience in handling Soc DPU Platform related tasks
Senior Manager, Networking Application Applicants are expected to have a solid experience in handling Networking Application related tasks
Research Scientist, Embodied and Agentic AI - New College Grad 2026 Applicants are expected to have a solid experience in handling Embodied and Agentic AI - New College Grad 2026 related tasks
Senior Product Manager, AI Infrastructure Software Applicants are expected to have a solid experience in handling AI Infrastructure Software related tasks
Manager, Internal Audit Applicants are expected to have a solid experience in handling Internal Audit related tasks
Senior Software Manager, Agentic AI Applicants are expected to have a solid experience in handling Agentic AI related tasks
Senior Software Engineer, GPU Communications and Networking Applicants are expected to have a solid experience in handling GPU Communications and Networking related tasks
Distinguished Engineer – High Performance AI Applicants are expected to have a solid experience in handling Job related tasks
Solutions Architect Applicants are expected to have a solid experience in handling Job related tasks
remote-jobserver Remote
Principal Developer Technology Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Software Engineer - GPU Platforms Applicants are expected to have a solid experience in handling Job related tasks
Technical Marketing Manager, Memory Technology Applicants are expected to have a solid experience in handling Memory Technology related tasks
Senior Workflow Specialist - Isaac Robotics Applicants are expected to have a solid experience in handling Job related tasks
Senior DFT Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
PCB Design Layout Engineer Applicants are expected to have a solid experience in handling Job related tasks
Manufacture System Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Test Development Engineer - DataCenter System Software Applicants are expected to have a solid experience in handling Job related tasks
Senior Deep Learning Framework Communications Engineer Applicants are expected to have a solid experience in handling Job related tasks
AI Scientist, Robotics Digital Twins - PhD New College Grad 2026 Applicants are expected to have a solid experience in handling Robotics Digital Twins - PhD New College Grad 2026 related tasks
Treasury Analyst MBA Intern – Summer 2026 Applicants are expected to have a solid experience in handling Job related tasks