Director, Chassis Design Verification job opportunity at Intel.

Home Jobs In India Tag: Chassis Design Verification Director, Chassis Design Verification position at Intel


DateMore Than 30 Days Ago bot
Intel Director, Chassis Design Verification
Experience: 18-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Chassis Design Verification

Copy Link Report
degreeMBA
loacation India, Bangalore, India
loacation India, Bangalo..........India

Job Details: Job Description:  Intel is seeking an experienced and highly technical Director of Chassis Design Verification for the Silicon Chassis team. In this strategic leadership role, you will drive the delivery of next-generation chassis IPs across multiple product families, building and mentoring a world-class verification team. You will architect comprehensive verification methodologies, lead technical development, and deliver first-pass silicon success through best-in-class IP design and verification practices. This role requires deep technical expertise across advanced DV methodologies and EDA tools, combined with extensive knowledge of interconnect protocols, cache coherency, memory architecture, and software integration. Responsibilities Lead, grow, and develop a high-performing functional verification team, providing strategic direction, technical mentorship, career development, and effective stakeholder management Define, develop, and deliver comprehensive verification methodology, environments, tools, and testplans that enable first-pass silicon success and continuous quality improvement Establish, monitor, and drive key quality metrics and KPIs; proactively identify, assess, and mitigate technical risks throughout the development lifecycle Collaborate closely with architecture, design, hardware design, and software teams from initial product definition through productization phases, ensuring optimal balance between complexity, schedule, and quality Ensure successful IP delivery to internal and external customers while managing competing requirements, schedules, and resources across multiple teams Qualifications: Minimum Qualifications BS/MS in Electrical Engineering, Computer Science, or related field, with 18+ years of relevant experience in design verification; extensive background in IP DV with demonstrated exposure to subsystem and SoC-level verification Proven deep expertise in interconnect protocols and memory subsystems, including AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; strong foundation in cache coherency models and memory consistency implementation Strong background in simulation-based verification methodologies including UVM, ABV, and co-simulation; proficiency in low-power verification techniques and industry-standard EDA tools Demonstrated experience collaborating with formal verification and emulation teams to develop and execute multimodal verification strategies 5+ years of proven success building, leading, and scaling verification teams in complex, high-impact programs Excellent communication and organizational skills with a demonstrated track record of delivering on-time, high-quality silicon and consistent customer satisfaction            Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location:  India, Bangalore Additional Locations: Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Other Ai Matches

Automation Software Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior AI SoC Architect Applicants are expected to have a solid experience in handling Job related tasks
APTM NPI Integrator Applicants are expected to have a solid experience in handling Job related tasks
High-Speed I/O PHY Architect Applicants are expected to have a solid experience in handling Job related tasks
Intern - Electrical Validation Engineer Applicants are expected to have a solid experience in handling Job related tasks
CPU Physical Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Manufacturing Operator (Nhân viên vận hành máy) Applicants are expected to have a solid experience in handling Job related tasks
IP/SOC Verification Engineer/Lead Applicants are expected to have a solid experience in handling Job related tasks
System Debugger Software Developer (m/f/d) Applicants are expected to have a solid experience in handling Job related tasks
IP Logic Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
DTCO Systems Analysis Engineer - Memory Applicants are expected to have a solid experience in handling Job related tasks
AI/GPU SoC Lead Applicants are expected to have a solid experience in handling Job related tasks
Packaging Module Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Operations Research, Engineering Analytics Intern Applicants are expected to have a solid experience in handling Engineering Analytics Intern related tasks
Project Controls Engineer (PCE) Applicants are expected to have a solid experience in handling Job related tasks
Senior Pre-Silicon Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Global Planning Analyst Applicants are expected to have a solid experience in handling Job related tasks
Lead Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Module Equipment Technician (Contract) Applicants are expected to have a solid experience in handling Job related tasks
Senior Formal Verification Engineer – AI SoC Development Applicants are expected to have a solid experience in handling Job related tasks
Human Resources Management Systems Analyst Applicants are expected to have a solid experience in handling Job related tasks
Sr. Compiler Engineer/Architect Applicants are expected to have a solid experience in handling Job related tasks
Power and Performance Design Engineer Applicants are expected to have a solid experience in handling Job related tasks