Multi-Project Wafer (MPW) Shuttle Program Manager job opportunity at Intel.

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Intel Multi-Project Wafer (MPW) Shuttle Program Manager
Experience: 1-years
Pattern: full-time
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loacation US, Oregon, Hillsboro, United States Of America
loacation US, Oregon, Hi..........United States Of America

Job Details: Job Description:  The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. Who we Are: As part of this team, you will help us grow our secure solution suite to meet U.S. Government requirements. The Intel Information Security organization is seeking a Multi-Project Wafer (MPW) Shuttle Program Manager. The candidate chosen for this role will manage a team of engineers working on design, architecture, and build secure classified infrastructure products to support USG operations. As a Multi-Project Wafer (MPW) Shuttle Program Manager you will play a pivotal role in overseeing and managing the execution of Multi-Project Wafer (MPW) Shuttles. The role involves strategic planning, risk management, and operational excellence to ensure seamless delivery of shuttles and high customer satisfaction. The successful candidate will work closely with cross-functional teams and subject matter experts from design database validation through packaged unit delivery, creating a collaborative environment to drive project success and continuous improvement. Key Responsibilities: Lead and execute multi-project shuttles across multiple Intel technologies, ensuring timely delivery and alignment with customer requirements. Develop and implement risk mitigation strategies to manage shuttle execution challenges. Enhance onboarding processes for first-time customers and streamline document management for ease of access and understanding. Optimize and Innovate strategies and BKMs for seamless execution of end-to-end Shuttle operations. Collaborate with and coordinate among multiple subject matter experts and cross-functional teams, including Tape-out, Frames, Fab, Die Prep, and Assembly teams, to ensure alignment and success in shuttle operations. Develop roadmaps and execute strategic objectives for future shuttle projects. Foster a customer-first attitude by maintaining strong relationships and delivering high-quality service. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.   Minimum Qualifications: US Citizenship. Ability to obtain and maintain an active US Government clearance (TS/SCI). Bachelor's with 4+ OR Master's with 3+ OR PhD with 1+ years experience and a degree in Engineering, Computer Science, or another STEM field of study. 3+ years experience of relevant experience in silicon design, engineering project management, semiconductor shuttle operations and/or a similar role. 3+ years experience risk management and operational planning. 3+ years experience project management skills. Preferred Qualifications: Active US Government Security Clearance. Bachelor's with 6+ OR Master's with 4+ OR PhD with 2+ years' experience and a degree in Engineering, Computer Science, or another STEM field of study. Familiarity with shuttle operations and Fab manufacturing processes Proven track record of enhancing operation excellence and working with cross-functional teams. Prior working experience with MPW / Shuttle or test chip design tapeout desired. Proven track record of technical leadership and project execution management in the complete life cycle of a Silicon on Chip (SoC) or similar products from definition to design and tape-out. Working fluency on process technology parameters, overall semiconductor manufacturing steps from design fracture through package assembly, process characterization, physical design rules/runset. Familiarity with database management for large, multi-site design projects. Working experiences of interfacing with process, design, and design automation teams. Good understanding of leading-edge process technologies, devices, and the interactions with circuit design. Familiar with SoC, CPU and custom (analog and digital) design styles, flows, tools, and methodologies. Familiar with EDA design software for VLSI layout and physical verification. Excellent communication and interpersonal skills, with the ability to work effectively with cross-functional teams.            Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location:  US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, San Jose Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .     Annual Salary Range for jobs which could be performed in the US: $133,800.00-255,200.00 USD     The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.     Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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