GPU Logic Design Engineer job opportunity at Intel.



DateMore Than 30 Days Ago bot
Intel GPU Logic Design Engineer
Experience: General
Pattern: full-time
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation US, California, Santa Clara, United States Of America
loacation US, California..........United States Of America

Job Details: Job Description:  Intel’s Discrete Graphics Engineering (DGE) organization develops cutting-edge discrete graphics products for gaming and AI. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products, including:  Creating a design to produce key assets that help improve product KPIs for discrete graphics products  Working with SoC Architecture and platform architecture teams to establish silicon requirements  Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule  Creating micro architectural specification document for the design.  Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.   Driving vendor's methodology to meet world class silicon design standards  Architecting area and power efficient low latency designs with scalabilities and flexibilities  Power and Area efficient RTL logic design and DV support  Running tools to ensure lint-free and CDC/RDC clean design, VCLP  Synthesis and timing constraints  Having achieved multiple tape-outs reaching production with first pass silicon  Ability to drive and improve digital design methodology to achieve high quality first silicon Hands on experience with FPGA emulation, silicon bring-up, characterization and debug  Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule  Strong verbal and written communication skills Good understanding of verilog and system verilog, synthesizable RTL  Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis  Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post silicon power correlation  Background in computer architecture  Bus fabric, including, but not limited to APB/AHB/AXI  Power management with multiple power domains, UPF, Power state tables.  Knowledge of lint tools, CDC and RDC tools, timing constraints, fishtail.  Knowledge of connectivity tools.  Understanding of key SoC design elements, arbiters, async FIFOs, DMAs, basic Controllers.  Comprehension of asynchronous clock crossing means and methodologies  Proven track record of bringing logic designs into high volume production  Ability to work well in a team and be productive under ambitious schedules  Should be self-motivated and well organized  Qualifications: BS+5 Years of relevant industry experience             Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location:  US, California, Santa Clara Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .     Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD     The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.     Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Other Ai Matches

Senior SOC Design Engineer - Physical Design and Integration Applicants are expected to have a solid experience in handling Job related tasks
Senior Pre-Silicon Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Executive Administrative Assistant to the Chief Marketing and Communications Officer Applicants are expected to have a solid experience in handling Job related tasks
MECOP Intern Applicants are expected to have a solid experience in handling Job related tasks
Graduate Talent (MPE DDG) Applicants are expected to have a solid experience in handling Job related tasks
Graduate Talent (MPE DDG) Applicants are expected to have a solid experience in handling Job related tasks
Senior SoC Physical Design Timing Engineer Applicants are expected to have a solid experience in handling Job related tasks
Cloud Software Developer Engineer Intern Applicants are expected to have a solid experience in handling Job related tasks
AI Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Supply Chain Engineer Applicants are expected to have a solid experience in handling Job related tasks
Development Tools Software Engineer- Intern Applicants are expected to have a solid experience in handling Job related tasks
Graduate Talent (MPE DDG) Applicants are expected to have a solid experience in handling Job related tasks
System Modeling and Specification Definition Student Applicants are expected to have a solid experience in handling Job related tasks
CPU Circuit Design Lead Applicants are expected to have a solid experience in handling Job related tasks
Director-Foundry Business Development Applicants are expected to have a solid experience in handling Job related tasks
TCAD Simulation Software and Modeling Engineer Applicants are expected to have a solid experience in handling Job related tasks
Equipment Engineer Applicants are expected to have a solid experience in handling Job related tasks
AI/ML Software Engineer Intern Applicants are expected to have a solid experience in handling Job related tasks
Software Engineer for VTC Simics development Applicants are expected to have a solid experience in handling Job related tasks
GPU Compiler Engineer Applicants are expected to have a solid experience in handling Job related tasks
Logistics Operations Manager Applicants are expected to have a solid experience in handling Job related tasks
Product Quality and Reliability Engineer Applicants are expected to have a solid experience in handling Job related tasks
Sales Marketing Commodity Manager Applicants are expected to have a solid experience in handling Job related tasks