E-Core CPU Design Automation Engineer job opportunity at Intel.

Home Jobs In Malaysia Tag: Job E-Core CPU Design Automation Engineer position at Intel


DatePosted 25 Days Ago bot
Intel E-Core CPU Design Automation Engineer
Experience: 3-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Malaysia, Penang, Malaysia
loacation Malaysia, Pena..........Malaysia

Job Details: Job Description:  E-core (formerly known as ATOM), Intel's most efficient CPU Technology team is looking for a highly motivated and technically savvy experienced individual to join our team as Design Automation Engineer. In this position, you will participate in the support and development of CAD solutions for the design of Intel products. Your responsibilities will include but will not be limited to: Defining, implementing and drive project execution by supporting the methodologies and EDA tools necessary to verify backend signoff flows using standard-cell based designs. Work closely with Physical Designers to drive solutions in 1 or more of areas, including Static Timing Analysis (STA), Formal-Equivalence Checking, Electrical Rule Checks (ERC), Static Noise analysis, Active/Dynamic/Leakage Power Analysis, LVS, Power-Rail Integrity, Extraction or ECO. Develops and tests Engineering Design Automation tools, creates flows/scripts to analyze and test design methodologies including driving new innovations to EDA tool vendors. Develop custom optimized solutions to address design requirements for leading-edge process technologies. Validate and drive continuous innovation of PDK technology, library files and other collaterals used for standard cell design, layout, and signoff with EDA CAD tools. Proficiency in benchmarking QOR and provide design guidance for better power optimization and/or techniques for frequency improvement and/or tool runtime improvement. Create flows/scripts to analyze, test and improve design methodologies, including through Machine Learning, and look for inefficiencies. Contribute to the development of multidimensional designs involving the layout of complex integrated circuits. Document and help with guidelines/specs. The ideal candidate should exhibit the following behavioral traits: Good inter-personal, clear communication and good teamwork skills. A can-do attitude driven by research and thriving on challenges. Self-motivator with strong problem - solving skills. Willing to handle multiple projects simultaneously and prioritize to project timelines. Good communicator who can accurately perform a deep dive to assess and summarize issues to management. Takes ownership to provide recommendations and drives solutions through to completion. Qualifications: Candidate must have a Bachelor's degree in Electrical/Computer Engineering with 3+ years of experience - OR - a Master's degree in Electrical/Computer Engineering with 2+ years of experience. Deep understanding of most, if not all Physical Design and Verification Tools, Flows and Methods used in VLSI back-end custom-transistor based designs. Expertise using industry standard Engineering Design Automation (EDA) VLSI tools from 1 or more of Synopsys, Cadence and/or Mentor Graphics in one of more of the following areas of: STA, Power, ECO, LVS, Power-rail integrity, Noise and/or ERC flows. Deep understanding and experience of signoff aspects in STA for timing closure (OCV, constraints, parasitics), LVS, Static Power Analysis or Signal integrity analysis (Noise, SI-crosstalk). Familiar with digital custom circuit transistor-level designs and topologies including dynamic circuit techniques and memories as well as SPICE models and netlists. Desire to deep-dive into timing paths, perform QOR difference analysis and identify key issues. Expertise with Linux environments and basic shell scripting. Expertise is a must in 1 or more scripting languages such as Python, Perl and/or Tcl. Knowledge in standard-cell liberty format syntax and digital circuit device-level SPICE modelling. Knowledge in standard formats from 1 or more of transistor-level netlist, standard parasitic formats and/or SDC constraints.- EDA tool Tcl API coding. Experience with advanced programming data structures. Preferred Qualifications: 1+ years of experience in one or more of the following: Cadence Virtuoso and/or SKILL coding. Leading/Mentoring junior team members or prior interns. Machine-learning/AI methods to solve complex problems dealing with automation of circuit design to aid in performance and power improvement. Timing and power ECO techniques and implementation.            Job Type: Experienced Hire Shift: Shift 1 (Malaysia) Primary Location:  Malaysia, Penang Additional Locations: Business group: The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Other Ai Matches

Senior Firmware Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Compiler Engineer Applicants are expected to have a solid experience in handling Job related tasks
APTM NPI Integrator Applicants are expected to have a solid experience in handling Job related tasks
Packaging Customer Engineer Applicants are expected to have a solid experience in handling Job related tasks
Pre-Silicon Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Silicon Design Engineering Manager – AI SoC Deployment Applicants are expected to have a solid experience in handling Job related tasks
ML Engineer, Demand and Supply Planning Applicants are expected to have a solid experience in handling Demand and Supply Planning related tasks
Power Delivery & System Validation Engineer (Intel Contract Employee) Applicants are expected to have a solid experience in handling Job related tasks
Materials Program Manager Intern Applicants are expected to have a solid experience in handling Job related tasks
TCAD Simulation Software and Modeling Engineer Applicants are expected to have a solid experience in handling Job related tasks
Module Equipment Technician (Contract) Applicants are expected to have a solid experience in handling Job related tasks
Optical Sub-System Architect – Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks
Security Researcher Applicants are expected to have a solid experience in handling Job related tasks
College Graduate Applicants are expected to have a solid experience in handling Job related tasks
Experienced Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
GenAI Software Solutions Engineer Applicants are expected to have a solid experience in handling Job related tasks
Cloud Software Developer Engineer Intern Applicants are expected to have a solid experience in handling Job related tasks
Neuromorphic Silicon Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Platform FW and AI application Engineer- Intern Applicants are expected to have a solid experience in handling Job related tasks
Manufacturing Operator (Nhân viên vận hành máy) Applicants are expected to have a solid experience in handling Job related tasks
Senior Verification Engineer – AI SoC Development Applicants are expected to have a solid experience in handling Job related tasks
Manufacturing Quality and Reliability Engineer Applicants are expected to have a solid experience in handling Job related tasks
GPU Physical Design Engineer Lead Applicants are expected to have a solid experience in handling Job related tasks