Sr. Compiler Engineer/Architect job opportunity at Intel.

Home Jobs In United States Of America Tag: Job Sr. Compiler Engineer/Architect position at Intel


DatePosted 25 Days Ago bot
Intel Sr. Compiler Engineer/Architect
Experience: 4-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation US, California, Santa Clara, United States Of America
loacation US, California..........United States Of America

Job Details: Job Description:  Join Us in Shaping the Future    At Intel, we are building the next generation of software innovation through the   oneAPI   software stack, a unified programming model designed to unlock the full potential of heterogeneous computing. Our team is at the forefront of enabling developers worldwide to harness CPUs, GPUs, and accelerators with   cutting-edge   tools, libraries, and compilers. By joining us,   you’ll   contribute to an open ecosystem that drives performance, scalability, and portability across diverse architectures—empowering breakthroughs in AI, HPC, and beyond. If   you’re   passionate about transforming how the world   computes   and want to work on technology that truly matters, this is your opportunity to make an impact.   The   Te am   The Intel Compiler Engineering Team is a high performing team responsible for the creation of the industry-leading Intel C/C++/DPC++ and Fortran Compilers, and is a leader in LLVM.org, the basis of our compiler products.  We are continually pushing the boundaries of compiler technology in support of providing maximally useful and performant compilers for all of Intel’s processor platforms, both CPU and GPUs.   Position Overview   We’re   hiring a Senior Compiler Architect to own the runtime architecture for Intel’s open ‑ source compiler stack (CPU + GPU/accelerators). You will set technical direction, design and evolve language runtimes, and lead delivery of new features that enable portable, high ‑ performance offload.   You ’ ll   drive upstream collaboration with LLVM.org, SYCL, and OpenMP,   l ead   development of novel optimization techniques for accelerated workloads . You will   define how our runtime integrates with the broader ecosystem, and ensure rock ‑ solid performance, reliability, and developer experience from silicon to software. This role is perfect for   individuals   who   thrive   on deep   systems   work, community leadership, and measurable impact on AI and HPC workloads.   Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.   Required Qualifications: BS with 8+ OR MS with 6+ OR PhD with 4+ years of experience with a degree in Computer Science or related field with focus on compiler development tools.   5+ years of hands-on compiler development experience  with a demonstrated history of technical contributions to LLVM.org (commit history, patches, reviews).   5+ years of experience with accelerated computing and parallel programming models working with GPU architecture. 5+ years of experience in compiler or application performance tuning to achieve   optimal   runtime and application throughput.      Preferred Qualifications: Hardware knowledge: understanding of modern CPU, GPU, and accelerator   architecture.   Ability to analyze and   optimize   language runtimes, scheduling, and memory models to achieve industry leading runtime and application performance across heterogeneous architectures (CPU, GPU, and accelerators).    Expert-level C/C++ with deep understanding of systems programming.   Patents or significant technical innovations in compiler technology.   Demonstrated cross-industry collaboration on language standards and specifications.              Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location:  US, California, Santa Clara Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, Massachusetts, Beaver Brook, US, Oregon, Hillsboro, US, Texas, Austin Business group: The Software Team drives customer value by enabling differentiated experiences through leadership AI technologies and foundational software stacks, products, and services. The group is responsible for developing the holistic strategy for client and data center software in collaboration with OSVs, ISVs, developers, partners and OEMs. The group delivers specialized NPU IP to enable the AI PC and GPU IP to support all of Intel's market segments. The group also has HW and SW engineering experts responsible for delivering IP, SOCs, runtimes, and platforms to support the CPU and GPU/accelerator roadmap, inclusive of integrated and discrete graphics. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .     Annual Salary Range for jobs which could be performed in the US: $173,660.00-330,340.00 USD     The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.     Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Other Ai Matches

AI Deployment Lead Applicants are expected to have a solid experience in handling Job related tasks
CPU-SoC Mask Layout Designer Applicants are expected to have a solid experience in handling Job related tasks
Contract Business Analyst - International Trade & SAP Applicants are expected to have a solid experience in handling Job related tasks
Electrical Validation Engineering Grad Intern Applicants are expected to have a solid experience in handling Job related tasks
Memory System Validation Engineer Applicants are expected to have a solid experience in handling Job related tasks
GPU Physical Design Engineer Lead Applicants are expected to have a solid experience in handling Job related tasks
Deep Learning Hardware Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
CMP Commodity Manager Applicants are expected to have a solid experience in handling Job related tasks
Business Strategist – Media & Entertainment Applicants are expected to have a solid experience in handling Job related tasks
E-Core CPU Design Automation Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Technical Expert - Manufacturing Integration Applicants are expected to have a solid experience in handling Job related tasks
Learning and Development Consultant Applicants are expected to have a solid experience in handling Job related tasks
Data Center Pre-Si FPGA Development Intern Applicants are expected to have a solid experience in handling Job related tasks
IT Infrastructure DevOps and SW Engineer Applicants are expected to have a solid experience in handling Job related tasks
Semiconductor Device Modeling Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Compiler Engineer Applicants are expected to have a solid experience in handling Job related tasks
Physical Design (Backend) Engineering Team Lead Applicants are expected to have a solid experience in handling Job related tasks
Senior Physical Design Application Engineer Applicants are expected to have a solid experience in handling Job related tasks
FVCTO - Formal Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Formal Verification Engineer – AI SoC Development Applicants are expected to have a solid experience in handling Job related tasks
Graduate Talent (MPE DDG) Applicants are expected to have a solid experience in handling Job related tasks
Lead Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Central Long Range Capacity Planning Sr. Analyst (Intel Foundry) Applicants are expected to have a solid experience in handling Job related tasks