Network Development Engineer, ML Infrastructure (High-Speed Interconnects) position at xAI.| United States Of America

xAI Network Development Engineer, ML Infrastructure (High-Speed Interconnects)

Experience: 8-years

Pattern: full-time

Country:

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Associate

Palo Alto, CA....United States Of America

About xAI xAI’s mission is to create AI systems that can accurately understand the universe and aid humanity in its pursuit of knowledge. Our team is small, highly motivated, and focused on engineering excellence. This organization is for individuals who appreciate challenging themselves and thrive on curiosity. We operate with a flat organizational structure. All employees are expected to be hands-on and to contribute directly to the company’s mission. Leadership is given to those who show initiative and consistently deliver excellence. Work ethic and strong prioritization skills are important. All employees are expected to have strong communication skills. They should be able to concisely and accurately share knowledge with their teammates. About the Role xAI is building at a furious pace with the latest compute and switching hardware to help people understand the universe. We are looking for exceptional ML Infrastructure Engineers with deep expertise in high-speed interconnect technologies to design, build, and optimize the network fabric that powers large-scale AI training and inference clusters. This strategic role will drive innovation in high-bandwidth, low-latency, power-efficient interconnects critical for AI/ML clusters based on advanced computing platforms. You will have the opportunity to work on all modalities of interconnects connecting GPUs and switches both inside and between data centers, including our primary front and backend networks that train Grok and that customers use for inference. Engineers will own all aspects from design and development to build and operations. You will be expected to define and improve team processes and to contribute to scaling and maintenance efforts. You will focus on the physical layer and system-level integration of copper (ACC, AEC, CPC) and optical (FRO, LRO/TRO, LPO, AOC, CPO) interconnects that directly determine the performance, power efficiency, scale, and cost of next-generation AI/ML clusters. This is a highly technical, hands-on role bridging ML cluster requirements with cutting-edge interconnect hardware — ideal for engineers who love both large-scale AI systems and the physics/engineering of 200G+ SerDes, PAM4, photonics, signal integrity and diagnostics. Responsibilities Design, validate, and productize high-speed copper and optical connectivity solutions for AI clusters (100k+ GPU scale). Own vendor due diligence and onboarding for new 1.6T products including AEC and pluggable optical transceivers (DR4/8, FR4) including rigorous bring-up & characterization. Investigate the opportunity for LPO and LRO in our network. Evaluate early co-packaged and near-packaged engines for switches and GPUs. Pathfinding for new interconnect modalities including VCSEL, microLED, THz radio-based solutions to improve network economics and reliability. Work closely with vendors (transceiver, cable, SerDes, DSP, silicon photonics foundries) to influence roadmaps and ensure timely delivery of next-gen solutions. Collaborate with ML training teams to translate workload communication patterns into concrete interconnect topology and optical reconfigurability requirements. Perform system-level simulation of end-to-end fabric performance. Drive failure analysis, root cause, and corrective actions for interconnect-related issues in production clusters through fleet-level metrics gathering and analysis. Contribute to internal tooling and automation for interconnect health monitoring, telemetry, diagnostics, remediation and automated qualification pipelines. Stay current with industry standards (OIF CMIS, IEEE) and emerging technologies (multi-core/hollow-core fiber, 448G SerDes, TFLN, ring resonators) Qualifications At least 8+ years of hands-on experience in designing, deploying and operating high-speed copper and optical interconnects, preferably in a module design role or in a hyperscale datacenter environment. Master's or PhD degree in Electrical Engineering, Photonics or Physics. Deep knowledge of PAM4 SerDes performance, equalization, jitter, crosstalk. Solid operational understanding of FEC, Retimers, TIAs and Drivers. Deep knowledge of optical link budget analysis and performance metrics including TDECQ, OMA, Tcode, stressed receiver sensitivity and associated diagnostics. Expertise in transceiver components including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, their failure modes and characterization. Knowledge of thermal, mechanical, power, signal integrity constraints in dense hardware. Knowledge of SiPh design process, yield improvement and reliability testing. Familiarity with CPO technologies and challenges/risk areas. Familiarity with subcomponent supply chains and global manufacturers, ODMs and CMs. Strong problem-solving skills and ability to thrive in a fast-paced, ambiguous setting. Location Work will be in-office, based out of Palo Alto, California. There will be occasional travel expected to Memphis, Tennessee for data center buildouts and to vendor locations for product and production-line due diligence. Interview Process After submitting your application, the team reviews your CV and statement of exceptional work. If your application passes this stage, you will be invited to an initial interview (45 minutes - 1 hour) during which a member of our team will ask some basic questions. If you clear the initial phone interview, you will enter the main process, which consists of four interviews: Interconnect technologies. Data center network architecture. Manager Interview. Meet and greet with the team with a presentation of a large scale solution or problem you owned, start to finish. Our goal is to finish the main process within one week. We don’t rely on recruiters for assessments. Every application is reviewed by a member of our technical team. All interviews will be conducted via Google Meet. Interested candidates should submit a resume highlighting specific interconnect projects (especially 400G+ copper/optical experience) and any large-scale cluster deployments. Why join our xAI team? Work on the interconnect fabric of the world’s largest and most advanced AI systems. Influence the physical-layer design of multi-billion-dollar-scale compute clusters. Opportunity to shape copper and optics strategy for the 1.6T → 3.2T transition. Direct impact on the next wave of frontier AI models. Annual Base Salary $180,000 - $440,000 USD Benefits Base salary is just one part of our total rewards package at X, which also includes equity, comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, and various other discounts and perks.xAI is an equal opportunity employer. For details on data processing, view our Recruitment Privacy Notice.

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Network Development Engineer, ML Infrastructure (High-Speed Interconnects) job opportunity at xAI.

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