Low power design engieer/micro-architect L5 job opportunity at DeepMind.

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DeepMind Low power design engieer/micro-architect L5
Experience: 7-years
Pattern: full-time
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Hiring inbound within New York City, New York, US

Snapshot At Google DeepMind, we've built a unique culture and work environment where long-term ambitious research can flourish. We are seeking a highly motivated Low Power Design Engineer / Micro-architect to join our team and contribute to the development of groundbreaking silicon for machine learning acceleration. About us Artificial Intelligence could be one of humanity’s most useful inventions. At Google DeepMind, we’re a team of scientists, engineers, machine learning experts and more, working together to advance the state of the art in artificial intelligence. We use our technologies for widespread public benefit and scientific discovery, and collaborate with others on critical challenges, ensuring safety and ethics are the highest priority. About you We seek out individuals who thrive in ambiguity and who are willing to help out with whatever moves silicon design and architecture forward. We regularly need to invent novel solutions to problems, and often change course if our ideas don’t work out, so flexibility and adaptability to work on any project is a must. You are a hands-on engineer with deep expertise in power-efficient design. The Role We are seeking a talented and highly motivated Low Power Design Engineer / Micro-architect to join our GenAI technical infrastructure research hardware team. You will be a hands-on technical leader responsible for steering the low-power design strategy and development for our custom silicon IPs, ensuring we meet our ambitious performance-per-watt goals. Responsibilities: Define and own the low-power micro-architecture for custom silicon IPs used in ML acceleration. Steer and actively participate in the development of low-power design techniques, from architectural conception through RTL implementation. Conduct hands-on analysis and optimization of power consumption, identifying and driving implementation of power-saving features (e.g., clock gating, power gating, dynamic voltage/frequency scaling). Collaborate with architecture, RTL, and physical design teams to establish power budgets and ensure low-power design intent is met. Work with verification teams to define and review low-power verification plans. Analyze power reports from synthesis, P&R, and power analysis tools to drive optimizations. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 7+ years of experience in ASIC design or micro-architecture, with a strong focus on low-power design. Hands-on experience with RTL design (Verilog/SystemVerilog). Deep understanding of low-power design techniques (e.g., multi-voltage domains, power gating, clock gating, DVFS). Experience with power analysis and estimation tools (e.g., PrimeTime-PX, PowerArtist, or similar). Preferred Qualifications: Master's or Ph.D. in a related field. Experience in developing and implementing low-power strategies for complex IPs, such as ML accelerators, GPUs, or high-performance compute blocks. Knowledge of micro-architecture trade-offs for performance, power, and area (PPA). Familiarity with UPF (Unified Power Format) and low-power verification methodologies. Good understanding of the full ASIC design flow, including physical design and verification impact.

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