Hardware Engineer || FPGA/Design Verifcation,UVM,UMM || Exp - 7 to 11 Years job opportunity at Cisco Systems.

Home Jobs In India Tag: UVM, UMM || Exp - 7 to 11 Years Hardware Engineer || FPGA/Design Verifcation,UVM,UMM || Exp - 7 to 11 Years position at Cisco Systems


DateMore Than 30 Days Ago bot
Cisco Systems Hardware Engineer || FPGA/Design Verifcation,UVM,UMM || Exp - 7 to 11 Years
Experience: 7-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

UVM, UMM || Exp - 7 to 11 Years

Copy Link Report
degreeOND
loacation Bangalore, India, India
loacation Bangalore, Ind..........India

Meet the Team We are part of the Hardware Platform Group, with our team specializing in FPGA verification. Our work spans both sophisticated data-path and challenging control-path FPGAs. The verification process includes crafting the DV architecture, test plan, and coverage plan, all the way through to final DV sign-off. We leverage industry-standard tools for simulation, linting, coverage, and assertions, incorporating various quality metrics to ensure a robust process. Our ultimate goal is to deliver bug-free RTL for first-pass success on the board. Additionally, we collaborate closely with our remote teams based in US and Italy. Your Impact * Lead and mentor a team of verification engineers, driving the development of robust test benches, coverage plans, and constrained random tests. * Ensure high-quality and reliable FPGA/ASIC designs through sophisticated verification techniques and comprehensive debugging. * Contribute to the adoption and evolution of ground breaking verification methodologies like UVM/VMM, improving team efficiency and performance. * Partner with architects, logic designers, and software engineers to align on architecture, micro-architecture, and system-level requirements. * Play a pivotal role in delivering next-generation, high-performance FPGA and ASIC products for Cisco’s networking solutions. * Ensure product reliability and performance, strengthening Cisco’s reputation and customer trust in its hardware solutions. Minimum Qualifications * Bachelor's Degree / Master's Degree in Electrical or Computer Engineering with 7+ years of experience in design verification. * Proficiency in OOPs, Verilog & System Verilog. * Confirmed verification skills : FPGA, planning, problem solving, debug, adversarial testing and random testing * Project based work experience with UVM/VMM methodologies. * You will have experience with architecting the testplan & test bench. Preferred Qualifications * Hands on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN etc. will be an added advantage. * Familiarity with VCS simulation flow, knowledge of coverage & assertions is desirable. Why Cisco?  At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.  We are Cisco, and our power starts with you. 

Other Ai Matches

AI Infrastructure Engineer - GoLang, Kubernetes, Dockers, Linux - 8-12 years Applicants are expected to have a solid experience in handling Kubernetes, Dockers, Linux - 8-12 years related tasks
Principal Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Technical Marketing Engineering Technical Leader Applicants are expected to have a solid experience in handling Job related tasks
Tech Lead, C++ Software Engineering Applicants are expected to have a solid experience in handling C++ Software Engineering related tasks
Paralegal: Splunk Product Legal (Hybrid) Applicants are expected to have a solid experience in handling Job related tasks
Customer Reliability Engineer Applicants are expected to have a solid experience in handling Job related tasks
Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Inside Account Executive (Cybersecurity) Applicants are expected to have a solid experience in handling Job related tasks
Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Account Executive - Portfolio Applicants are expected to have a solid experience in handling Job related tasks
Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Solutions Engineer Applicants are expected to have a solid experience in handling Job related tasks
Support Engineer I (Intern) - United States Applicants are expected to have a solid experience in handling Job related tasks
Account Executive – MM Applicants are expected to have a solid experience in handling Job related tasks
Hardware Engineer I (Intern) - United States Applicants are expected to have a solid experience in handling Job related tasks
Inside Account Executive Applicants are expected to have a solid experience in handling Job related tasks
Software Engineer intern – Indexing & Clustering, Australia Applicants are expected to have a solid experience in handling Australia related tasks
Account Executive - Splunk Federal Civilian - Treasury Applicants are expected to have a solid experience in handling Job related tasks
Hardware Engineering Technical Leader - High Speed Board Design (12 to 16 yrs) Applicants are expected to have a solid experience in handling Job related tasks
C++ Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Site Reliability Engineer Applicants are expected to have a solid experience in handling Job related tasks