Director, Hardware Engineering position at Cisco Systems.| United States Of America

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Cisco Systems Director, Hardware Engineering

Experience: 12-years

Pattern: full-time

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San Jose, Cali..........United States Of America

The application window is expected to close on: Dec 30th, 12 PM ET 2025 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team Our team owns the global test strategy, execution, and leadership for Cisco’s flagship Silicon One portfolio across wafer, device, and system levels. We are seeking an accomplished Director of Test Engineering to oversee this. This role blends deep semiconductor test expertise with organizational leadership, long-term strategic planning, and multi-functional influence at scale. Your Impact Organizational & Leadership Responsibilities: 1) Lead, scale, and mentor a global organization of test engineering managers and engineers spanning post-silicon validation, ATE test development, and system-level testing. 2) Build organizational capability through hiring, mentoring, succession planning, and leadership development. 3) Foster a culture of innovation, accountability, operational rigor, and engineering excellence. Test Strategy, Architecture & Execution: 1) Own the end-to-end test engineering strategy for Silicon One across wafer sort, final test, and system-level test. 2) Drive long-term roadmaps for automated test systems, silicon validation methodologies, and infrastructure improvements. 3) Define scalable test strategies that ensure quality, coverage, yield, cost efficiency, and high-volume manufacturability. 4) Guide the development and deployment of automated test solutions for pre-silicon emulation, post-silicon bring-up, device characterization, reliability screening, and production test. 5) Provide technical leadership in Design for Test (DFT), scan/ATPG, analog/mixed-signal test, high-speed SERDES bring-up and validation, and defect and failure analysis. Technical Guidance & Silicon Debug: 1) Direct teams performing silicon bring-up, root-cause debugging, HW/SW integration, ATE program development, and diagnostic automation. 2) Oversee development of test content, test hardware/fixtures, and overall tester architecture for advanced networking silicon. 3) Champion the use of data analysis, analytics, and yield management systems to identify systemic issues, optimize test efficiency, and drive yield improvement. Multi-functional Collaboration: 1) Partner closely with silicon architecture, ASIC design, verification, software, reliability, manufacturing operations, and product engineering teams to ensure seamless test integration throughout the product lifecycle. 2) Engage with contract manufacturers, OSATs, ATE vendors, and ecosystem partners to ensure robust test execution and technology alignment. 3) Represent the test engineering organization in executive forums, providing clear updates on readiness, risks, important metrics, and strategic direction. Process, Efficiency & Continuous Improvement: 1) Define and track KPIs for test quality, yield, coverage, and throughput. Continuously improve test methodologies through innovation, new technologies, automation, and industry guidelines. 2) Drive efficiency initiatives to reduce test time, optimize cost of test, and increase throughput without sacrificing quality. Leadership Skills: 1) Ability to inspire, develop, and retain high-performing engineering teams. Strong execution subject area and operational rigor in managing complex, multi-program environments. 2) Experience collaborating with senior executives, external partners, and global collaborators. Other Key Skills: 1) Excellent communication and executive presence. 2) Strategic problem solver with strong analytical and problem-solving skills. 3) Adaptability to changing priorities in a fast-paced product development environment. Minimum Qualifications Education: BSc or MSc in Electrical Engineering, Computer Engineering, Computer Science, Materials Science, or related field. 12+ years in semiconductor, system-level, or silicon test engineering. 5+ years leading engineering managers or global test teams. Strong expertise in ATE (testers/handlers/probers), test hardware design, and high-volume manufacturing test flows. Proven experience in DFT, scan/ATPG, mixed-signal validation, SERDES testing, and post-silicon bring-up. Strong background in test automation, Python-based test development, and Linux-based workflows. Preferred Qualifications Successful track record leading global test operations through NPI to mature high-volume manufacturing. Demonstrable ability to resolve complex silicon defects and guide corrective action processes. Demonstrated impact on yield ramp, test efficiency, and cost optimization across multiple product generations. Experience introducing new test technologies, analytics platforms, or automation frameworks at scale. Ability to influence at senior leadership levels and drive cross-organizational alignment. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $230,100.00 to $325,300.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $230,100.00 - $374,100.00 Non-Metro New York state & Washington state: $216,500.00 - $337,000.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Director, Hardware Engineering job opportunity at Cisco Systems.

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