Analog Design Engineer, Sr. Principal job opportunity at Marvell Technology, Inc..



bot
Marvell Technology, Inc. Analog Design Engineer, Sr. Principal
Experience: 10-years
Pattern: full-time
apply Apply Now
Salary:
Status:

Sr. Principal

Copy Link Report
degreeOND
loacation Santa Clara, CA, United States Of America
loacation Santa Clara, C..........United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As an Analog IC Design Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of an analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects. What You Can Expect The candidate should be very familiar with SERDES design and will be leading high-speed and high-performance SerDes development in advanced technology nodes, 3nm, 2nm and beyond. Participate in SerDes Architecture Development with DSP, Analog and Digital design teams. Analog circuit design, such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.). New technique development for next generation TX/RX/PLL Working with validation team for testing plan, IP characterization and debug Silicon supporting for product and customer What We're Looking For Master’s degree or PhD in Electrical Engineering with 10+ years experience Strong knowledge on the deep sub-micron CMOS technologies. E xperience in designing mixed signal circuits including ADCs, DACs, RX, TX, PLLs, Filters, Bandgap bias circuits, regulators, and other analog circuits. Knowledge and Experience on low power and high-speed design techniques. Excellent problem solving, and analytical skills are essential. Strong knowledge on IC design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc. Lab testing skills to evaluate the prototype unit to the design specification. Expected Base Pay Range (USD) 190,460 - 285,300, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-TD1

Other Ai Matches

Embedded Software Intern Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer- AI/ML Software & Compilers Applicants are expected to have a solid experience in handling Job related tasks
Engineering Program Manager / Project Manager Applicants are expected to have a solid experience in handling Job related tasks
Advanced Package Technology Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Principal Software Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
Director of Product Marketing Applicants are expected to have a solid experience in handling Job related tasks
Senior Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Application Engineer Intern - Master's Degree (RDSS 2026) Applicants are expected to have a solid experience in handling Job related tasks
Engineering Project Management Intern (AMS COMPHY) Applicants are expected to have a solid experience in handling Job related tasks
Application Engineer, Customer Success - Entry Level Professional (ELP) Applicants are expected to have a solid experience in handling Customer Success - Entry Level Professional (ELP) related tasks
Network Platform Development Engineer (Switch, SAI, NOS/SDK, Routing/Tunneling/Overlay protocols, L2/L3 Development, C, Linux Kernel, DPDK) Applicants are expected to have a solid experience in handling SAI, NOS/SDK, Routing/Tunneling/Overlay protocols, L2/L3 Development, C, Linux Kernel, DPDK) related tasks
Sr. Principal Engineer, Advanced Packaging Applicants are expected to have a solid experience in handling Advanced Packaging related tasks
Staff Product Engineer Applicants are expected to have a solid experience in handling Job related tasks
DSP Custom Digital Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Principal Hardware Validation Applicants are expected to have a solid experience in handling Job related tasks
remote-jobserver Remote
Suzhou_Staff Sofware/Firmware Engineer, FAE Applicants are expected to have a solid experience in handling FAE related tasks
Staff Engineer, Analog Layout Applicants are expected to have a solid experience in handling Analog Layout related tasks
Staff Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Senior Analog/Mixed-Signal Design Engineer - RF/SiPho/TIA/CMOS/SiGe Applicants are expected to have a solid experience in handling Job related tasks
Principal Engineer-Analog Circuit Design Applicants are expected to have a solid experience in handling Job related tasks
Director Product Management - CXL Applicants are expected to have a solid experience in handling Job related tasks
Analog/RF Design Engineer Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Principal/Staff Engineer, DFT Engineering Applicants are expected to have a solid experience in handling DFT Engineering related tasks