Senior Principal Engineer - Design For Test (DFT) job opportunity at Marvell Technology, Inc..

Home Jobs In United States Of America Tag: Job Senior Principal Engineer - Design For Test (DFT) position at Marvell Technology, Inc.


bot
Marvell Technology, Inc. Senior Principal Engineer - Design For Test (DFT)
Experience: 15-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Morrisville, NC, United States Of America
loacation Morrisville, N..........United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a Digital IC Design Senior Principal Engineer with Marvell, you’ll be a member of the Custom Silicon Engineering team. This team is a leader in large multi-die designs that are driving high compute performance and acceleration in many markets, including custom AI, 5G and 6G. The role will be challenging and will require an experienced DFT engineer that can work with existing DFT solutions while also creating new solutions to address industry first issues. What You Can Expect The position will be responsible for architecting, leading and implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs The execution involves Design-for-Test architecture definition, implementation of various DFT/DFX features, validation, IP-DFT, STA, pattern generation & post-silicon bring-up and debug for various designs/IPs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What We're Looking For Bachelor’s, Master’s degree or PhD in Computer Science, Electrical Engineering or related fields with minimum of 15 years of work experience. Direct DFT experience with at least 12 years in the custom chip design business Led the DFT execution on several ASICs.  Was responsible for all DFT execution functions from architecture definition to tape out through silicon bring-up. Hands-on working experience in various stages of DFT-Execution: SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bring-up/Debug Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least five monolithic designs.  These designs should have been at or approaching reticle limits. Thorough knowledge on various DFT/Test architecture solutions for 2.5D/3D IC design and should be involved in DFT-Architecture definition of at-least couple of MCM designs. Strong fundamentals in digital circuit design and logic design Understanding of DFT flows and methodologies and experience with Siemens/Synopsys Tool set (Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC) Proven track record of problem solving and innovation to meet challenging design requirements. Excellent team player and can work with different function leaders, across different geographies to define and execute the DFT project to completion.   Excellent communications skill both verbal and written. Scripting skills using Python, PERL, Tcl and C-Shell is plus. Expected Base Pay Range (USD) 170,800 - 252,750, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-NF1

Other Ai Matches

Advanced Packaging Technology Pathfinding and Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Emulation Intern Applicants are expected to have a solid experience in handling Job related tasks
Senior Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Principal Engineer-Analog Circuit Design Applicants are expected to have a solid experience in handling Job related tasks
SYN/STA Engineering Intern (Optical PHY) Applicants are expected to have a solid experience in handling Job related tasks
Principal Architect & Lead Engineer – Enterprise AI Platforms Applicants are expected to have a solid experience in handling Job related tasks
Senior Principal Software Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
Software/Firmware Engineer (Senior Staff/Principal) Applicants are expected to have a solid experience in handling Job related tasks
Validation Engineer (C, Python, Ethernet PHY Testing, Networking L1, L2, L3 (SAI), Switch) Applicants are expected to have a solid experience in handling Python, Ethernet PHY Testing, Networking L1, L2, L3 (SAI), Switch) related tasks
Analog Engineer Intern - PhD Applicants are expected to have a solid experience in handling Job related tasks
Senior Procurement Manager - OSAT Applicants are expected to have a solid experience in handling Job related tasks
Product Security Compliance Engineer (FIPS, Crypto, Common Criteria, OCP-SAFE, C) Applicants are expected to have a solid experience in handling Crypto, Common Criteria, OCP-SAFE, C) related tasks
Design Verification Senior Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks
remote-jobserver Remote
Senior Staff Sales Applicants are expected to have a solid experience in handling Job related tasks
Network Platform Development Engineer (Switch, SAI, NOS/SDK, Routing/Tunneling/Overlay protocols, L2/L3 Development, C, Linux Kernel, DPDK) Applicants are expected to have a solid experience in handling SAI, NOS/SDK, Routing/Tunneling/Overlay protocols, L2/L3 Development, C, Linux Kernel, DPDK) related tasks
Associate Vice President, Chief of Staff - Custom Cloud Solutions Applicants are expected to have a solid experience in handling Chief of Staff - Custom Cloud Solutions related tasks
Digital Design (Senior to Senior Staff level) Applicants are expected to have a solid experience in handling Job related tasks
SEV Validation Senior Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Application Engineer, Customer Success - Entry Level Professional (ELP) Applicants are expected to have a solid experience in handling Customer Success - Entry Level Professional (ELP) related tasks
Senior Principal Digital IC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Staff Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal Technical IP Engineer - Manage 3rd Party IP Integration - DDR/LPDDR/GDDR/HBM/eMMC memory Applicants are expected to have a solid experience in handling Job related tasks
Distinguished Engineer: Advanced Optical Engines Applicants are expected to have a solid experience in handling Job related tasks