Principal Silicon Validation Engineer job opportunity at Marvell Technology, Inc..



bot
Marvell Technology, Inc. Principal Silicon Validation Engineer
Experience: 15-years
Pattern: full-time
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Santa Clara, CA, United States Of America
loacation Santa Clara, C..........United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Validation Engineer: Responsible for bring up, debug and characterize silicon level Marvell’s internal IPs such as High-Speed SerDes, PLL/DLL, ADC, etc. in various Marvell products. Evaluate and debug new features in PHY, develop driver firmware, collect performance data, and resolve application/production issues including SAS and PCIe products. Support internal SoC, FAE and ATE team on testing and system level debugging. Provide direct technical support to top tier customers and work with them to review designs, discuss questions and help tune performance to meet system requirement. Work includes but not limited to develop and execute bench level validation test plans, develop script to automate testing, generate appropriate test report and write application notes. Provide technical support to customers. Act as a primary technical interface between the company and customers. Qualify design activity at the customer engineering level and participate in the definition of new products and the identification of niche areas that present new opportunities for Marvell. Make new product recommendations to Design/Marketing teams at Marvell. What You Can Expect . Responsible for bring up, debug and characterize silicon level Marvell’s internal IPs such as High-Speed SerDes, PLL/DLL, ADC, etc. in various Marvell products.   Evaluate and debug new features in PHY, develop driver firmware, collect performance data, and resolve application/production issues including SAS and PCIe products.   Support internal SoC, FAE and ATE team on testing and system level debugging.   Provide direct technical support to top tier customers and work with them to review designs, discuss questions and help tune performance to meet system requirement.   Develop and execute bench level validation test plans, develop script to automate testing, generate appropriate test report and write application notes.   Provide technical support to customers. Act as a primary technical interface between the company and customers. Qualify design activity at the customer engineering level and participate in the definition of new products and the identification of niche areas that present new opportunities for Marvell. Strategize and communicate new product recommendations to Design/Marketing teams at Marvell. Oversee and manage all aspects of projects, from conception to completion. Ensure that each project meets its individual goals and objectives. What We're Looking For As a Principal Silicon Validation Engineer at Marvell, you’ll be helping to deliver high bandwidth over long distances. This team performs analog validations on amplifiers that drive optical electronic devices and receivers. We also validate silicon photonics, do upper electronic measurements and support the coherent digital signal programming unit. This is a niche area at Marvell, working with cutting edge technologies used by many internal and external customers around the world. Requirements: Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. Proficiency in silicon validation of mixed signal/analog/digital ICs and blocks is required. Must be adept in handling lab equipment like oscilloscopes, network analyzers, etc. Knowledgeable in writing simple and clear technical reports. Familiar with Python Programming. Expertise in Project Management to handle multiple projects simultaneously, setting deadlines and ensuring teams achieve them. Proven track record of engineering leadership roles. Expected Base Pay Range (USD) 143,200 - 214,500, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-NF1

Other Ai Matches

Advanced Packaging Technology Pathfinding and Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Emulation Intern Applicants are expected to have a solid experience in handling Job related tasks
Senior Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Principal Engineer-Analog Circuit Design Applicants are expected to have a solid experience in handling Job related tasks
SYN/STA Engineering Intern (Optical PHY) Applicants are expected to have a solid experience in handling Job related tasks
Principal Architect & Lead Engineer – Enterprise AI Platforms Applicants are expected to have a solid experience in handling Job related tasks
Senior Principal Software Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
Software/Firmware Engineer (Senior Staff/Principal) Applicants are expected to have a solid experience in handling Job related tasks
Validation Engineer (C, Python, Ethernet PHY Testing, Networking L1, L2, L3 (SAI), Switch) Applicants are expected to have a solid experience in handling Python, Ethernet PHY Testing, Networking L1, L2, L3 (SAI), Switch) related tasks
Analog Engineer Intern - PhD Applicants are expected to have a solid experience in handling Job related tasks
Senior Procurement Manager - OSAT Applicants are expected to have a solid experience in handling Job related tasks
Product Security Compliance Engineer (FIPS, Crypto, Common Criteria, OCP-SAFE, C) Applicants are expected to have a solid experience in handling Crypto, Common Criteria, OCP-SAFE, C) related tasks
Design Verification Senior Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks
remote-jobserver Remote
Senior Staff Sales Applicants are expected to have a solid experience in handling Job related tasks
Network Platform Development Engineer (Switch, SAI, NOS/SDK, Routing/Tunneling/Overlay protocols, L2/L3 Development, C, Linux Kernel, DPDK) Applicants are expected to have a solid experience in handling SAI, NOS/SDK, Routing/Tunneling/Overlay protocols, L2/L3 Development, C, Linux Kernel, DPDK) related tasks
Associate Vice President, Chief of Staff - Custom Cloud Solutions Applicants are expected to have a solid experience in handling Chief of Staff - Custom Cloud Solutions related tasks
Digital Design (Senior to Senior Staff level) Applicants are expected to have a solid experience in handling Job related tasks
SEV Validation Senior Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Application Engineer, Customer Success - Entry Level Professional (ELP) Applicants are expected to have a solid experience in handling Customer Success - Entry Level Professional (ELP) related tasks
Senior Principal Digital IC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Staff Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal Technical IP Engineer - Manage 3rd Party IP Integration - DDR/LPDDR/GDDR/HBM/eMMC memory Applicants are expected to have a solid experience in handling Job related tasks
Distinguished Engineer: Advanced Optical Engines Applicants are expected to have a solid experience in handling Job related tasks