Digital IC Design Staff Engineer job opportunity at Marvell Technology, Inc..

Home Jobs In United States Of America Tag: Job Digital IC Design Staff Engineer position at Marvell Technology, Inc.


bot
Marvell Technology, Inc. Digital IC Design Staff Engineer
Experience: 5-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Santa Clara, CA, United States Of America
loacation Santa Clara, C..........United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a Digital IC Design Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers. What You Can Expect Design and integrate IPs for System-on-Chip SoC solutions using state-of-art IC design methodologies, clock domain crossing (CDC)-based design and application-specific integrated circuit (ASIC) design flows. Perform RTL coding and functional verification of design on block and system level using Verilog and hardware description language (HDL). Perform synthesis and timing closure. Analyze and develop the functionality of IC design by utilizing the knowledge of logic design and related very-large-scale integration (VLSI) architecture, SCAN/design for testing (DFT) methodology, and test patterns. Provide design documentation, description and requirements to Application Engineers, Test Engineers, and/or customers. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience. Proficiency in the following skill sets gained during professional or academic experience: RTL design, Verilog and/or SystemVerilog; Synthesis tools such as Synopsys Design Compiler; Clock Domain Crossing; Scripting/programming language with at least one of the following: PERL, Python, TCL, C/C++. STA and timing closure; Lower power design techniques. Expected Base Pay Range (USD) 105,470 - 158,000, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-NF1

Other Ai Matches

Validation Intern - Bachelor's Degree Applicants are expected to have a solid experience in handling Job related tasks
Global Program Manager L&D Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Senior to Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Silicon Validation Engineer Applicants are expected to have a solid experience in handling Job related tasks
remote-jobserver Remote
Suzhou_Staff Sofware/Firmware Engineer, FAE Applicants are expected to have a solid experience in handling FAE related tasks
SYN/STA Engineering Intern (Optical PHY) Applicants are expected to have a solid experience in handling Job related tasks
Global Compensation Program Manager Applicants are expected to have a solid experience in handling Job related tasks
Principal Analog Mixed-Signal IC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Demand Planner Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Software Developer Engineer in Test Applicants are expected to have a solid experience in handling Job related tasks
Principal Technical IP Engineer - Manage 3rd Party IP Integration - DDR/LPDDR/GDDR/HBM/eMMC memory Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Intern (AMS COMPHY) Applicants are expected to have a solid experience in handling Job related tasks
Analog Layout Engineer Intern Applicants are expected to have a solid experience in handling Job related tasks
Analog IC Design, Principal Engineer Applicants are expected to have a solid experience in handling Principal Engineer related tasks
Staff Engineer, Analog Layout Applicants are expected to have a solid experience in handling Analog Layout related tasks
Analog Layout Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Senior Staff Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Principal Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Engineering Project Manager Applicants are expected to have a solid experience in handling Job related tasks
Demand Planning Analyst Intern - Bachelor's Degree Applicants are expected to have a solid experience in handling Job related tasks