Principal Engineer, Hardware & Silicon Validation job opportunity at Marvell Technology, Inc..

Home Jobs In Singapore Tag: Hardware & Silicon Validation Principal Engineer, Hardware & Silicon Validation position at Marvell Technology, Inc.


bot
Marvell Technology, Inc. Principal Engineer, Hardware & Silicon Validation
Experience: 12-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Hardware & Silicon Validation

Copy Link Report
degreeBachelor's (B.A.)
loacation Singapore, Singapore
loacation Singapore....Singapore

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a Hardware and Silicon Validation Principal Engineer at Marvell, you’ll be helping to deliver high bandwidth over long distances. This team performs analog validations on amplifiers that drive optical electronic devices and receivers. We also validate silicon photonics, do upper electronic measurements and support the coherent digital signal programming unit. This is a niche area at Marvell, working with cutting edge technologies used by many internal and external customers around the world. What You Can Expect Complete responsibility of PHY Validation in post-silicon environment Defining, documenting, executing, and reporting the overall PHY validation/test plan for Marvell storage devices Lab-based silicon bring-up and unit test execution focused on Physical and PCS layer hardware and firmware functionality Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER Analyze and debug issues on Phy protocol of storage interface (SATA, SAS, PCIe, Ethernet) Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers Lead collaborative technical discussions to drive resolution on technical issues Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to Ethernet/PCIe PHY Work closely with customers to address design issue and debug failure cases What We're Looking For Bachelor of Science in Electrical Engineering with 10-12 years of relevant work experience, or Master of Science in Electrical Engineering with more than 10 years of relevant work experience preferred. Strong understanding of high-speed SERDES, equalization technique and any high-speed standard (IEEE802.3, PCIe, DP, etc.) Proven experience in High-Speed IO testing, debugging and validation, strong lab skills with hands on experience, in system bring up, system testing and debug. In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.). Working knowledge of IEEE 802.3 400G/800G/1.6T interface and characterization Working knowledge of board design; able to read board schematics and board layout. Knowledge in SERDES modeling techniques and proven experience working with Perl or Python. Working knowledge and experience on PCIe and/or SAS/SATA SERDES and extensive knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is a definite plus. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-ST1

Other Ai Matches

Senior Principal Analog Mixed Signal IC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Staff Phy Embedded Device Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Package Development, Signal Integrity and Power Integrity Engineer, Staff Applicants are expected to have a solid experience in handling Signal Integrity and Power Integrity Engineer, Staff related tasks
Senior Principal Technical Program Manager - AI Custom Silicon Solutions Applicants are expected to have a solid experience in handling Job related tasks
Optical Engineer, Senior Staff Applicants are expected to have a solid experience in handling Senior Staff related tasks
Regional IT Service Delivery Engineer (Staff Professional) Applicants are expected to have a solid experience in handling Job related tasks
Senior Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Senior Staff Manager, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Field Application Engineering, Principal Engineer Applicants are expected to have a solid experience in handling Principal Engineer related tasks
Director Analyst Relations Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Analog Mixed-Signal Design Engineer - RF/TIA/SiGe/CMOS Applicants are expected to have a solid experience in handling Job related tasks
Physical Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Sales Operations/Cloud Business Manager Applicants are expected to have a solid experience in handling Job related tasks
Sr Staff Design Verification Engineer (DDR/LPDDR/HBM) Applicants are expected to have a solid experience in handling Job related tasks
Analog/Mixed-Signal IC & AI Systems R&D Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Engineering IP Program Manager, Sr. Principal Applicants are expected to have a solid experience in handling Sr. Principal related tasks
Architecture Validation (L2, L3, Python automation, Device modeling) Applicants are expected to have a solid experience in handling L3, Python automation, Device modeling) related tasks
Principal Engineer, Design Verification Applicants are expected to have a solid experience in handling Design Verification related tasks
Senior Staff Engineer - RTL ASIC Design Applicants are expected to have a solid experience in handling Job related tasks
Senior Silicon Validation Engineer Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Memory Layout Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer - SerDes Digital Design Applicants are expected to have a solid experience in handling Job related tasks