Engineering IP Program Manager, Sr. Principal job opportunity at Marvell Technology, Inc..

Home Jobs In United States Of America Tag: Sr. Principal Engineering IP Program Manager, Sr. Principal position at Marvell Technology, Inc.


bot
Marvell Technology, Inc. Engineering IP Program Manager, Sr. Principal
Experience: 15-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Sr. Principal

Copy Link Report
degreeOND
loacation Santa Clara, CA, United States Of America
loacation Santa Clara, C..........United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact The IP program Manager will be part of Central Engineering’s program management team responsible for the IP development and delivery for Marvell’s products and custom silicon businesses, giving the opportunity to contribute to the successes of numerous Marvell programs. What You Can Expect The successful candidate will understand the SoC IP needs and develop plans to deliver and support the IP from conception through to program Mass Production Release (MPR).  The successful candidate will have both depth and breadth in the related IP engineering that involve cross functional organizations, in the forms of analog, logic, design for test, layout, timing, validation, PnR, etc.  Good understanding of technologies and IP development process and methodology are required. Excellent interpersonal skills and communication skills are a must.  Overall responsibility for program management of IP development & delivery to Marvell product business units  Drive closure of IP specs & requirements  Demonstrated strong cross-functional leadership to chair weekly cross functional meetings assessing status, milestones, and completeness of plans with regular program updates to Marvell Executive stakeholders  Support Marvell’s Program Management Processes  Matrixed leadership of engineering managers distributed across the engineering organization IP Silicon validation responsibility is required Execute lessons learned, risk management, and enforce agreed to processes  Responsibility for the successful outcome of IP development & delivery  What We're Looking For BS in Electrical Engineering with MSEE preferred  Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience, OR Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 5 -10 years of experience.  6+ years of experience as an Engineering Project Manager in the Semiconductor industry preferred  6+ years of experience as a mixed signal IP designer Preferred experience as a mixed signal design manager. Knowledge of SoC/IC design flow for advanced process technologies and process flows and methodologies in Silicon Development     Excellent verbal and written communication and presentation skills     Demonstrated ability to partner with technical managers to drive projects to completion        Demonstrated effective partnerships and relationships with key stakeholders    Excellent leadership skills   Must have a broad background in ASIC or other Microelectronics semiconductor product development  Expected Base Pay Range (USD) 163,940 - 245,600, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AP1

Other Ai Matches

Principal Supply Chain Program Manager - Design Applicants are expected to have a solid experience in handling Job related tasks
Product Engineer Intern - Bachelor's Degree Applicants are expected to have a solid experience in handling Job related tasks
Software Developer Engineer in Test Applicants are expected to have a solid experience in handling Job related tasks
Principle FAE, ASIC Applicants are expected to have a solid experience in handling ASIC related tasks
Analog Intern - PhD Applicants are expected to have a solid experience in handling Job related tasks
Engineering Project Management Intern (Connectivity) Applicants are expected to have a solid experience in handling Job related tasks
Senior Manager Firmware Development Applicants are expected to have a solid experience in handling Job related tasks
AI Platform Engineer Intern (Agentic) - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Principal Product Manager Custom Cloud Solutions Silicon/Semiconductor IP Product Manager Applicants are expected to have a solid experience in handling Job related tasks
Staff Phy Embedded Device Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Security Developer (C, Linux, System Security, Embedded programming) Applicants are expected to have a solid experience in handling Linux, System Security, Embedded programming) related tasks
Senior Principal Software Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
AI Development Intern Applicants are expected to have a solid experience in handling Job related tasks
Staff Engineer, RTL Design Applicants are expected to have a solid experience in handling RTL Design related tasks
Staff/Sr. Staff Field Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
Systems Application Engineer Applicants are expected to have a solid experience in handling Job related tasks
Optical Engineer, Senior Staff Applicants are expected to have a solid experience in handling Senior Staff related tasks
Analog Layout Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Physical Design Intern Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Senior Staff ASIC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Staff Physical Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Packaging EDA Automations Manager Applicants are expected to have a solid experience in handling Job related tasks