Digital IC Principal Design Engineer job opportunity at Marvell Technology, Inc..

Home Jobs In United States Of America Tag: Job Digital IC Principal Design Engineer position at Marvell Technology, Inc.


bot
Marvell Technology, Inc. Digital IC Principal Design Engineer
Experience: 15-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Santa Clara, CA, United States Of America
loacation Santa Clara, C..........United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a Digital IC Design Principal Engineer at Marvell, you will be a member of the Custom Compute Solution IP development team. This team develops uniquely high-performance signal processing datapaths and compute acceleration logic for Marvell's custom silicon SoCs. We are seeking an experienced problem solver who enjoys innovating solutions to address cutting-edge challenges in the industry. The customers served by this team are often other chip companies and major technology firms—well-known names to all candidates. What You Can Expect Oversee a team of engineers to develop and verify RTL design for CPU subsystems, co-processor/accelerator data path circuits, and high-speed DSP data path. Take ownership of design IP including updating, maintaining, and enhancing the current IP. Responsibilities include: Define VLSI architecture. Implement RTL design. Verify design functionality. Collaborate with verification engineer to develop exhaustive test cases to ensure successful design. Work closely with the design verification and architecture teams to resolve silicon, design, and verification issues. Mentor, guide, and train engineers who are working on the team. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. Possess strong technical leadership skills with expertise in RTL design, data path, VLSI architecture, and EDA tools. Possess strong analytical and critical thinking skills. Strong knowledge of UNIX/Linux operating systems. Experienced in VLSI architecture definition and System Verilog RTL development. Proficiency in scripting languages such as Shell script, Perl, Tcl, or Python. Experience in Verilog simulator, synthesis tools, timing analysis tools, and RTL status check tools. Excellent communication and presentation skills. Experience in applying AI tools to RTL design is preferred. Expected Base Pay Range (USD) 146,850 - 220,000, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-NF1

Other Ai Matches

Principal DSP Firmware Engineer - Embedded Processors/Mixed Signal /RTOS/PHY Applicants are expected to have a solid experience in handling Job related tasks
Senior Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Senior Principal Switch Architect Applicants are expected to have a solid experience in handling Job related tasks
Lab Manager Applicants are expected to have a solid experience in handling Job related tasks
Global Program Manager L&D Applicants are expected to have a solid experience in handling Job related tasks
Principal Engineer, System Design and Validation Applicants are expected to have a solid experience in handling System Design and Validation related tasks
PHY Digital Lead Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer, Hardware & Silicon Validation Applicants are expected to have a solid experience in handling Hardware & Silicon Validation related tasks
Site HR Manager Applicants are expected to have a solid experience in handling Job related tasks
Analog IC Design Intern (COMPHY) Applicants are expected to have a solid experience in handling Job related tasks
DFT Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal Digital IC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Software Engineer Intern (Application) Applicants are expected to have a solid experience in handling Job related tasks
SYN/STA Engineer Intern (CCS) Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Senior Principal Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Hardware Validation (Test Solutions) Engineer Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Optical Product Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Field Application Engineer - Connectivity Applicants are expected to have a solid experience in handling Job related tasks
Staff Engineer, Hardware Design Applicants are expected to have a solid experience in handling Hardware Design related tasks
Marketing Operations Intern - Bachelor's Degree Applicants are expected to have a solid experience in handling Job related tasks
Principal Technical IP Engineer - Manage 3rd Party IP Integration - DDR/LPDDR/GDDR/HBM/eMMC memory Applicants are expected to have a solid experience in handling Job related tasks