Senior Staff Hardware Design Engineer - PCB Board Level Circuit Design Simulation Test job opportunity at Marvell Technology, Inc..

Home Jobs In United States Of America Tag: Job Senior Staff Hardware Design Engineer - PCB Board Level Circuit Design Simulation Test position at Marvell Technology, Inc.


bot
Marvell Technology, Inc. Senior Staff Hardware Design Engineer - PCB Board Level Circuit Design Simulation Test
Experience: 3-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeBachelor's (B.A.)
loacation Santa Clara, CA, United States Of America
loacation Santa Clara, C..........United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Design and architecture for Central Engineering hardware, Hardware development for on-board subsystems to support chip test infrastructure. You will participate in hardware board development, lab testing and chip level bring up activities. Central Engineering is the center hub providing advanced silicon IP to be used by all the other fast growing business units including Data Center, Enterprise, Optics, Custom Computing, Storage and Networking. You’ll be part of the printed circuit board (PCB) engineering team designing hardware for many different projects at Marvell. Marvell is developing state of the art complex chips and hardware for Data Center applications and you will be exposed to leading edge technologies and have the opportunity be part of this high growth and innovative environment. What You Can Expect Create and review schematics and PCB layout and provide design constraints to layout. Evaluate and select new components such as power supplies, power FETs, low jitter Clocks, logic IC, etc. Create spice simulation test benches for power and control circuits. Collaborate with internal firmware/software teams on implementing board level and Chip diagnostics using Python. Lab bring up and board level test/debug on new PCB hardware. FPGA designs using Verilog. What We're Looking For Bachelor CE/EE degree (MS preferred) in Electrical Engineering, with 3+ years of experience in data communication systems or similar field. Must have experience in board level circuit design, simulation and hands-on test and board bringup. Proficiency in OrCad Capture, Cadence Allegro, Python environments. Strong Knowledge in signal and power integrity for high speed PCB designs for network applications. Understanding of the PCB fab and assembly processes for engineering protos. Proficiency with lab test equipment (Scopes, VNA, TDR). knowledge in FPGA and Verilog a plus Ability to communicate well and work closely and cross-functionally with engineering groups in resolving issues Expected Base Pay Range (USD) 121,400 - 181,800, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AP1

Other Ai Matches

Senior Principal Analog Mixed Signal IC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Staff Phy Embedded Device Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Package Development, Signal Integrity and Power Integrity Engineer, Staff Applicants are expected to have a solid experience in handling Signal Integrity and Power Integrity Engineer, Staff related tasks
Senior Principal Technical Program Manager - AI Custom Silicon Solutions Applicants are expected to have a solid experience in handling Job related tasks
Optical Engineer, Senior Staff Applicants are expected to have a solid experience in handling Senior Staff related tasks
Regional IT Service Delivery Engineer (Staff Professional) Applicants are expected to have a solid experience in handling Job related tasks
Senior Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Senior Staff Manager, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Field Application Engineering, Principal Engineer Applicants are expected to have a solid experience in handling Principal Engineer related tasks
Director Analyst Relations Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Analog Mixed-Signal Design Engineer - RF/TIA/SiGe/CMOS Applicants are expected to have a solid experience in handling Job related tasks
Physical Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Sales Operations/Cloud Business Manager Applicants are expected to have a solid experience in handling Job related tasks
Sr Staff Design Verification Engineer (DDR/LPDDR/HBM) Applicants are expected to have a solid experience in handling Job related tasks
Analog/Mixed-Signal IC & AI Systems R&D Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Engineering IP Program Manager, Sr. Principal Applicants are expected to have a solid experience in handling Sr. Principal related tasks
Architecture Validation (L2, L3, Python automation, Device modeling) Applicants are expected to have a solid experience in handling L3, Python automation, Device modeling) related tasks
Principal Engineer, Design Verification Applicants are expected to have a solid experience in handling Design Verification related tasks
Senior Staff Engineer - RTL ASIC Design Applicants are expected to have a solid experience in handling Job related tasks
Senior Silicon Validation Engineer Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Memory Layout Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer - SerDes Digital Design Applicants are expected to have a solid experience in handling Job related tasks