PHY Digital Lead job opportunity at Marvell Technology, Inc..



bot
Marvell Technology, Inc. PHY Digital Lead
Experience: 15-years
Pattern: full-time
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeAssociate
loacation Bangalore, India
loacation Bangalore....India

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a Digital IC Design Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. What You Can Expect As a Principal Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs for the up and coming UCIe IP roadmap. Additional responsibilities will include, but not be limited to: • Responsible for micro-architecture design and development of SOC and associated component IP like Memory Controllers/PCIE interface/CXL interfaces etc. • Working with Architects and Verification engineers to deliver develop complex, high performance and timing critical designs through all aspects of the SoC front-end design flow (incl. timing closure and power optimization) What We're Looking For • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. • Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. • Strong understanding of SoC architecture, processor cores, memory and peripheral interfaces through hands on prior experience. • Extensive experience in Verilog/VHDL, Spyglass and Quality checks of the implemented RTL for LINT, CDC. • Hands on experience in interpretive language such as Perl/Python. • Proven track record of delivering production-quality designs on aggressive development schedules. • Domain expertise in UCIe, CXL/PCIe protocols, DDR memory controllers is a plus. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-RV1

Other Ai Matches

Senior Principal Analog Mixed Signal IC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Staff Phy Embedded Device Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Package Development, Signal Integrity and Power Integrity Engineer, Staff Applicants are expected to have a solid experience in handling Signal Integrity and Power Integrity Engineer, Staff related tasks
Senior Principal Technical Program Manager - AI Custom Silicon Solutions Applicants are expected to have a solid experience in handling Job related tasks
Optical Engineer, Senior Staff Applicants are expected to have a solid experience in handling Senior Staff related tasks
Regional IT Service Delivery Engineer (Staff Professional) Applicants are expected to have a solid experience in handling Job related tasks
Senior Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Senior Staff Manager, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Field Application Engineering, Principal Engineer Applicants are expected to have a solid experience in handling Principal Engineer related tasks
Director Analyst Relations Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Analog Mixed-Signal Design Engineer - RF/TIA/SiGe/CMOS Applicants are expected to have a solid experience in handling Job related tasks
Physical Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Sales Operations/Cloud Business Manager Applicants are expected to have a solid experience in handling Job related tasks
Sr Staff Design Verification Engineer (DDR/LPDDR/HBM) Applicants are expected to have a solid experience in handling Job related tasks
Analog/Mixed-Signal IC & AI Systems R&D Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Engineering IP Program Manager, Sr. Principal Applicants are expected to have a solid experience in handling Sr. Principal related tasks
Architecture Validation (L2, L3, Python automation, Device modeling) Applicants are expected to have a solid experience in handling L3, Python automation, Device modeling) related tasks
Principal Engineer, Design Verification Applicants are expected to have a solid experience in handling Design Verification related tasks
Senior Staff Engineer - RTL ASIC Design Applicants are expected to have a solid experience in handling Job related tasks
Senior Silicon Validation Engineer Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Memory Layout Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer - SerDes Digital Design Applicants are expected to have a solid experience in handling Job related tasks