DFT Principal Engineer job opportunity at Marvell Technology, Inc..

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Marvell Technology, Inc. DFT Principal Engineer
Experience: 12-years
Pattern: full-time
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loacation Petah-Tikva, Israel
loacation Petah-Tikva....Israel

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a DFT Principal Engineer with Marvell, you’ll be a member of the DFX Engineering team in NSX Business group. DFT/DFx (Design for Test) team is a critical part of our innovation in semiconductor technology, focusing on ensuring the reliability and testability of our advanced networking solutions. Our team is dedicated to developing and implementing cutting-edge DFT methodologies that enhance the quality and performance of Marvell products. What You Can Expect As a member of the DFX team, you will be responsible for major DFX disciplines execution (ATPG, MBIST, DFX Verification, STA sign off) and post si activities. In this role you will act as DFX owner for the whole project or major DFX disciplines and will work closely with SoC Architecture, Design, Verification, Backend and post-silicon teams, taking into account all aspects of ASIC flow and full range of pre-Si and post Si activities. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields Over 12 years of proven experience in ASIC VLSI design and verification. Strong knowledge of DFT design and understanding of DFT techniques and methodologies, including JTAG and iJTAG protocols and architecture, SCAN, MBIST, and BScan Experience in SoC flows, silicon bring-up, and silicon debug activities. Extensive experience with EDA tools (e.g., Cadence, Synopsys, Siemens/Mentor Graphics). Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion Experience with DFT techniques and tools, synthesis, simulation, and verification flows. Experience in leading DFT activities throughout an ASIC development flow. Strong analytical and problem-solving skills, ability to work independently and managing multiple tasks effectively Strong debugging capabilities to identify and resolve design issues. Experience with low power design techniques and methodologies. Thoroughness and attention to detail in all aspects of design and verification. Expertise in RTL design using Verilog/SystemVerilog - strong advantage Good learning skills, ability to see a broad picture Team work oriented - Communicative, will to learn from others, good personal relations and working relations within a team. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AB1

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