Design-for-Test (DFT) Engineering Intern job opportunity at Marvell Technology, Inc..



bot
Marvell Technology, Inc. Design-for-Test (DFT) Engineering Intern
Experience: General
Pattern: full-time
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Ho Chi Minh, Vietnam
loacation Ho Chi Minh....Vietnam

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact At Marvell, ss part of DCE-CCS-Hardware DFT group, we take all responsibility for Test Solutions from Architecture, Implementation, Verification before Tape Out and validation post Tape Out to enable Marvell products to reach Mass Production Readiness. This is more than a typical internship—it’s a launchpad of your career as you are expected to not only learn and develop your technical competencies, but also integrate into Marvell's core behaviors and working culture that drives innovation and leading innovation in the industry. You’ll gain hands-on experience, receive mentorship from industry leaders, and contribute to real projects that drive Marvell’s product and R&D roadmap. What You Can Expect To fully understand ASIC design flow and DFT in ASIC to production To acquire basic DFT flow with EDA tools and be able to support basic DFT tasks, using Marvell standard flow for Logic Scan and Memory BIST solutions To joint develop a working solution with latest EDA tool DFT feature to serve to need test solutions for datacenter/AI xPU Why This Internship Matters This internship will give you: Real project experience in one of the world’s leading chip design environments Exposure to Marvell’s core technologies, toolchains, and product workflows A mentorship path that could evolve into a full-time role or thesis opportunity Your Path Forward Many of our interns go on to become key contributors and technical leaders within Marvell. If you’re dreaming of a career that contributes to the significant growth of AI Accelerate Infrastructure—this is where you start. What We're Looking For In final year of university program in Computer Science, Electrical Engineering or related fields, or the equivalent work experience that provides knowledge and exposure to theories, principles and concepts. Having basic knowledge of digital logic design, Verilog HDL and digital simulation tools Having basic knowledge of IC manufacturing, silicon defects and testing Detail oriented, self-motivated team worker, good verbal and written communication skills Good scripting/programming skill and familiar with Unix/Linux environment Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-HP1

Other Ai Matches

Principal Analog Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff ASIC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Staff/ Senior Staff QA Engineer (Storage, CXL, PCIE) Applicants are expected to have a solid experience in handling CXL, PCIE) related tasks
Design Verification Senior Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
AI Development Intern Applicants are expected to have a solid experience in handling Job related tasks
Senior Physical Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Principal Technical Program Manager - AI Custom Silicon Solutions Applicants are expected to have a solid experience in handling Job related tasks
Advanced Packaging SI/PI Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal Signal Integrity Engineer Applicants are expected to have a solid experience in handling Job related tasks
Staff Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
SYN/STA Engineer Intern (CCS) Applicants are expected to have a solid experience in handling Job related tasks
Staff Analog Layout Engineer Applicants are expected to have a solid experience in handling Job related tasks
Software Engineer Intern - Bachelor's Degree Applicants are expected to have a solid experience in handling Job related tasks
Analog Layout Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Analog IC Design Engineer Intern Applicants are expected to have a solid experience in handling Job related tasks
System Design and Silicon Validation Intern (Connectivity) Applicants are expected to have a solid experience in handling Job related tasks
Principal Product Engineer Applicants are expected to have a solid experience in handling Job related tasks
CAD Engineer, AI Based Automation Development Applicants are expected to have a solid experience in handling AI Based Automation Development related tasks
Silicon Photonics Engineer Applicants are expected to have a solid experience in handling Job related tasks
Hardware Validation (Test Solutions) Engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal Engineer Physical Design Applicants are expected to have a solid experience in handling Job related tasks