Senior Staff Engineer - RTL ASIC Design job opportunity at Marvell Technology, Inc..

Home Jobs In India Tag: Job Senior Staff Engineer - RTL ASIC Design position at Marvell Technology, Inc.


bot
Marvell Technology, Inc. Senior Staff Engineer - RTL ASIC Design
Experience: 10-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Bangalore, India
loacation Bangalore....India

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a Digital IC Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect Work with the Architecture team as a design-team member to shape the micro-architecture of the IP/block. Write specifications for the relevant block, microarchitecture of one or more blocks. Implement a specification using RTL coding techniques and best practices Work with the physical design teams for synthesis and timing signoff. Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip simulation plus debug. What We're Looking For Bachelor’s degree in computer science, electrical engineering, or related fields and 8-10 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 6-8 years of experience. Excellent Logic design and debug skills; knowledgeable in bus protocols like AHB/AXI/I2C/UART RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level function verification.  Hands-on experience in front-end design tools and methodologies is a must.  Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-RV1

Other Ai Matches

Demand Planning Analyst Intern - Bachelor's Degree Applicants are expected to have a solid experience in handling Job related tasks
Principal Hardware Engineer, Optics Applicants are expected to have a solid experience in handling Optics related tasks
Staff Validation Engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Principal/Staff Engineer, DFT Engineering Applicants are expected to have a solid experience in handling DFT Engineering related tasks
SEV Validation Senior Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Director Information Technology Applicants are expected to have a solid experience in handling Job related tasks
Analog IC Design Intern (COMPHY) Applicants are expected to have a solid experience in handling Job related tasks
Staff Engineer, Analog Layout Applicants are expected to have a solid experience in handling Analog Layout related tasks
System Engineer Intern (Optical DSP) - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer - SerDes Digital Design Applicants are expected to have a solid experience in handling Job related tasks
Staff Engineer- Analog Design Applicants are expected to have a solid experience in handling Job related tasks
Design Verification (Senior to Staff Engineer) Applicants are expected to have a solid experience in handling Job related tasks
Analog Layout Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Analog Layout Intern - Bachelor's Degree Applicants are expected to have a solid experience in handling Job related tasks
Senior Principal Applications Engineering - Network Validation Applicants are expected to have a solid experience in handling Job related tasks
System Engineer - Optical DSP Intern - PhD Applicants are expected to have a solid experience in handling Job related tasks
SERDES Validation Director Applicants are expected to have a solid experience in handling Job related tasks
Design Verification - Manager Applicants are expected to have a solid experience in handling Job related tasks
Staff Engineer, Quality Assurance (Cryptography, Cloud HSM, C/Python automation, KMS) Applicants are expected to have a solid experience in handling Quality Assurance (Cryptography, Cloud HSM, C/Python automation, KMS) related tasks
Hardware Validation Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Signal Integrity Engineer Intern (Cloud Platform Optics) - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer, Optical Applicants are expected to have a solid experience in handling Optical related tasks