Advanced Packaging Technology Pathfinding and Development Engineer position at Marvell Technology, Inc..| United States Of America

Marvell Technology, Inc. Advanced Packaging Technology Pathfinding and Development Engineer

Experience: 15-years

Pattern: full-time

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Austin, TX....United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Advanced Packaging R&D team is responsible for package design and technology development to meet the electrical, mechanical, thermal and system requirements for the next generation high performance computing (HPC), Artificial Intelligence (AI) and networking solutions. The group focuses on signal integrity, power integrity, thermal integrity, mechanical integrity, processability, manufacturability, and reliability, involving high speed signaling and complex power delivery networks (PDNs) requiring innovative and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip, multiple component configurations involving, but not limited to, 2.5D and 3D packages, Co-packaged copper or optics and advanced substrates. Marvell has partnered with the world's leading manufacturers to solve our customer’s most challenging designs and integrations with industry-leading packaging technologies. What You Can Expect Develop packaging technology roadmap for AI XPU, XPU-attach and Switch Explore technologies beyond what is currently available, make recommendations, and create and protect IP to maximize performance. Create new package technology concepts from open ended ideas, perform routing feasibility, signal and power integrity studies for design optimization. Explore technology feasibility and create proof-of-concept samples and productize technologies. Define package architecture including chiplet topology, interposer/substrate scaling, power delivery network strategy, and thermal design envelope. Lead co-design efforts across silicon design, floorplanning, PDN modeling, and mechanical/thermal reliability. Lead package material selection, substrate stack-up definition, mechanical modeling, and reliability analysis. Partner with silicon design teams to co-optimize die floorplan, bump map, TSV, and RDL requirements. Work with OSATs / Foundry partners to evaluate process capability, manufacturability, yield, and cost. Drive package qualification and reliability validation to volume readiness. What We're Looking For Experience in advanced package and substrate technologies with deep understanding of process and materials, component and board level reliability, warpage and thermal management. Experience in managing substrate and assembly material vendors, substrate manufacturers, OSATs and foundries. Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as design methodology and strategies. Experience in signal and power integrity simulations, analysis and optimization for 2.5D and 3D packages including interface with memory, interposer, substrates and PCBs. Ability to determine optimal signal routing, power delivery verification and package size determination Bachelor’s degree in mechanical engineering, material science or related fields and 15+ years of related professional experience or master’s degree and 12+ years of related professional experience or PhD degree / post-doc with 8+ years of experience. Experience interfacing with product design teams for optimized floor-planning, package related design input and power delivery network design. Bachelor's degree in electrical engineering or related fields and 15+ years of related professional experience in signal and power integrity, or master’s degree and 10+ years of related professional experience, or PhD degree with 8+ years of experience. Skills needed to be successful in this role: Ability to develop an idea into a proof of concept and then a proof of concept into a productizable technology Deep understanding of fundamental concepts of signal and power integrity, transmission line and electromigration, and the ability to apply those concepts to create new design rules and explore new technologies utilizing current baseline for 2.5D/3D package technology including (a) CoWoS-S/R/L, (b) EMIB-T, (c) CPO, (d) CPC. Mastery in tools and workflows to guide and enable the team on what sims need to be run: previous hands-on experience with signal and power integrity analyses using Cadence Sigrity PowerSI and Ansys SIwave; EM sims using Ansys HFSS, SI-Wave, Cadence Clarity, and the ability to correlate that with real world challenges is a required skill. Good understanding of interposer, substrate, package, PCB level design rules, ability to perform routing feasibility studies using Cadence APD or PCB editor. Good understanding of chip-package interactions and failure mechanism at component and board level, thermal and warpage management. Ability to manage programs involving cross-functional teams. Strong interpersonal skills and willingness to learn new things are necessary along with the ability to work with stakeholders in multiple time zones across the globe. Ability to influence vendors to align their roadmap with company goals. Strong communication, presentation and documentation skills The ideal candidate would have: Prior experience in data center AI accelerators, networking silicon, or custom HPC silicon. Board, system and rack level integration, thermal, mechanical, signal and power analysis. Ability to influence senior stakeholders across architecture, silicon design, system platform engineering, and supply chain Experience setting roadmaps, not just executing them. Experience with silicon disaggregation and reaggregation and memory integration. Demonstrated leadership driving cross-company supplier programs. Experience with VNA and TDR measurements for package and PCB characterization Experience in advanced package and substrate technologies with understanding of process and materials, component and board level reliability, warpage and thermal management. Expected Base Pay Range (USD) 170,800 - 252,750, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-MM1

Advanced Packaging Technology Pathfinding and Development Engineer job opportunity at Marvell Technology, Inc..

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