Memory Layout Engineer job opportunity at Capgemini SE.

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Capgemini SE Memory Layout Engineer
Experience: Professional
Pattern: Permanent
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Hiring inbound within Bangalore

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.Job Description About the JobChoosing Capgemini means choosing a place where you’ll be empowered to shape your career, supported by a collaborative global community, and inspired to reimagine what’s possible. Join us in helping leading Consumer Products and Retail Services (CPRS) organizations unlock the value of technology and drive scalable, sustainable growth.Your RoleAs a Memory/Custom Layout Design Engineer, you will be responsible for designing high-performance memory leafcell layout libraries from scratch and integrating them at the top level. You will work on advanced FinFET technologies and ensure optimized layout design for performance, reliability, and manufacturability.In this role, you will:Design memory leafcell layout libraries from scratch, including top-level integrationApply knowledge of various memory architectures to layout designOptimize layout for performance, area, and reliabilityWork with FinFET technology, understanding DRC limitations and layout constraintsPerform physical verification and debug issues related to DRC, LVS, ERC, and boundary conditionsRun and fix issues related to EM and IR analysisUse Cadence Virtuoso for layout editing and Calibre for physical verificationYour Profile4–10years of experience in Memory or Custom Layout DesignStrong understanding of memory architectures and layout optimization techniquesHands-on experience with FinFET technology and DRC rulesProficient in physical verification flows (DRC, LVS, ERC) and debuggingExperience with EM/IR analysis and fixesSkilled in Cadence Virtuoso and Calibre toolsFamiliarity with scripting languages for automation and flow customizationBachelor’s degree (B.E/B.Tech) in Engineering or related fieldWhat You’ll Love About Working HereYou’ll be part of a cutting-edge design team working on advanced semiconductor technologies. We offer a collaborative environment, opportunities for technical growth, and exposure to industry-leading tools and methodologies. Our culture supports innovation, learning, and excellenceAbout UsAt Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the sameCapgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.

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