Design Verification Boost job opportunity at Capgemini SE.

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Capgemini SE Design Verification Boost
Experience: Professional
Pattern: Permanent
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Job DescriptionTeam Leadership: Lead and manage a team of verification engineers.Verification Strategy: Define strategies for verifying IPs and SoCs to ensure first silicon success.Test Planning & Development:Write test plans.Develop test benches and test cases.Coverage-Driven Verification:Use industry-standard methodologies (likely UVM/SystemVerilog).Focus on functional coverage, code coverage, and assertions..Job Description - Grade SpecificYour Profile:You will be part of the team verifying IPs and SoCs leading to first Si success.Manage and lead a team of Verification engineersIP verification is coverage driven using latest industry standard methodologies and HVLs.Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases.Code coverage, Functional coverage and assertions are desired.ARM based SoC verification experience is an added advantage.Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus.Multiple positions with emphasis on AMS and Power aware verification.Should have worked on GLS.Primary SkillsVerilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting – Perl, Python, Shell, and Tcl.Secondary SkillsTest bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR

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