Silicon Design Engineer (Power Technical Lead) job opportunity at Altera Corporation.

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Altera Corporation Silicon Design Engineer (Power Technical Lead)
Experience: 10-years
Pattern: full-time
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loacation San Jose, California, United States, United States Of America
loacation San Jose, Cali..........United States Of America

Job Details: Job Description: About the Company Altera is one of the world's leading providers of programmable solutions. With a renewed focus on agility, software-first, and AI-driven solutions, Altera is shaping the future of computing by providing flexible technology, empowering innovators with scalable products, from high-performance to power- and cost-optimized devices for cloud, network, and edge applications. Join us in our journey to becoming the #1 FPGA provider in the world as we redefine the next era of programmable innovations! About the Team & Role As part of the Power and Performance Team, you'll be surrounded by some of the brightest minds in the world as we work across the Altera Engineering team to achieve Performance per Watt leadership for every product in our broad portfolio. As a Silicon Design Engineer (Power Technical Lead) , you will have the opportunity to drive full chip and sub-system level power analysis and optimization on our next generation FPGA products. You’ll set power targets, analyze pre-silicon power, oversee power model generation and methodology, and identify critical power optimization opportunities.  In this high-impact role, you will collaborate closely with cross-functional teams (Architecture, Design, Planning, Package, Platform).  You will help define flows to enable efficient and accurate power analysis, including workload- and profile-dependent scenarios.  If you have a passion for low power design and optimization, we would love to talk with you! The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. Salary Range $178.9k - $259.0k USD Qualifications: What We Want to See 10+ years of hands-on hardware design experience, including experience in one or more of the following: Power optimization over full product development cycle Low power circuit design, including some analog Timing sign-off analysis Power optimization techniques such as profiling, clock-gating, power-gating, etc. Power-related EDA tools such as PTPX, Redhawk, and Power Artist Familiarity with PrimeTime, Design Compiler, PnR, UPF, etc. Ways to Stand Out from the Crowd (Experience in one or more of the following preferred qualifications is considered a plus factor): 15+ years of experience in a hardware design related role Post-silicon power correlation experience FPGA and related EDA tools (Quartus/Vivado) Flow or tool development using Python/Perl/Tcl Master’s or PhD Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. Education Requirement Bachelor’s Degree (or higher) in Electrical Engineering, Computer Engineering, Computer Science, or related field. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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