Physical Design Implementation Lead - ML/AI focused  job opportunity at Altera Corporation.

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Altera Corporation Physical Design Implementation Lead - ML/AI focused 
Experience: 10-years
Pattern: full-time
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loacation San Jose, California, United States, United States Of America
loacation San Jose, Cali..........United States Of America

Job Details: Job Description: About Altera Accelerating Innovators — Altera provides leadership programmable solutions that are easy to use and deploy, across the cloud to the edge, enabling limitless possibilities for AI. Our broad portfolio includes FPGAs, SoCs, CPLDs, IP, development tools, system-on-modules, SmartNICs and IPUs, offering the flexibility to accelerate innovation.  Our innovation in programmable logic began in 1983. Since then we’ve delivered the tools and technologies that empower customers to innovate, differentiate, and succeed in their markets.  Join us on our journey to becoming the world’s #1 FPGA company! Why Join Altera? At Altera, you’ll be part of a team that’s redefining programmable logic and accelerating innovation across industries. We offer a dynamic work environment, cutting-edge technology, and opportunities to grow your career while shaping the future of compute. About the Role: Altera is seeking a Physical Design Implementation Lead - ML/AI focused to join our SoC Physical Design Team! Own and drive full-chip implementation from RTL to GDSII, including timing closure, power optimization, and physical verification. Collaborate with RTL, DFT, STA, and packaging teams to ensure seamless integration and convergence across domains. Develop and maintain automation scripts (Tcl, Python, Perl, etc.) to enhance productivity and flow robustness. Evaluate and integrate EDA tools and methodologies to improve design efficiency and QoR. Lead technical reviews and provide guidance to design teams on best practices and flow usage. Analyze design metrics and debug complex issues across the physical design flow. Drive innovation in physical design methodologies to meet aggressive PPA and schedule targets. Salary Range     The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences , trainings , etc. We also offer incentive opportunities that reward employees based on individual and company performance.    $142,600 - $206,500 USD We use artificial intelligence to screen, assess, or select applicants for the position.   Qualifications: Required Qualifications: BS/MS or PhD in Electrical Engineering, Computer Engineering, or related field. 10+ years of hands-on experience in physical design implementation and flow development. Expert-level knowledge of industry-standard EDA tools (Synopsys, Cadence, Siemens). Strong scripting skills in Tcl, Python, Perl, and shell. Proven experience in full-chip implementation and tapeout of complex SoCs or FPGAs. Deep understanding of timing, power, signal integrity, and physical verification. Excellent problem-solving, communication, and leadership skills. Preferred Qualifications: Experience with hierarchical design methodologies and physical IP integration. Familiarity with advanced process nodes Knowledge of machine learning techniques applied to EDA flows is a plus. Prior experience in FPGA architecture or design is highly desirable. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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