Senior Static Timing Analysis (STA) Developer job opportunity at Altera Corporation.

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Altera Corporation Senior Static Timing Analysis (STA) Developer
Experience: 10-years
Pattern: full-time
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loacation San Jose, California, United States, United States Of America
loacation San Jose, Cali..........United States Of America

Job Details: Job Description: We are seeking an experienced Senior Static Timing Analysis (STA) Developer to architect, design, and optimize next‑generation timing analysis engines for advanced ASIC and FPGA design flows. This role is ideal for someone who has deep expertise in STA algorithms, large‑scale EDA software development, and performance‑driven optimization. You will play a key role in building industry‑leading STA solutions capable of handling massive SoC designs, complex clocking structures, and modern multi‑threaded compute environments. Key Responsibilities Core STA Engine Development Architect and develop high‑performance STA engines for ASIC and FPGA design flows. Enhance graph‑based timing analysis algorithms to support complex clock trees, timing exceptions, and multi‑domain clocking. Improve path search algorithms to reduce memory footprint and accelerate timing path generation. Ensure high correlation and competitive performance relative to industry‑leading STA tools. Performance, Scalability & Optimization Identify and eliminate runtime bottlenecks across timing and logic optimization flows. Optimize PPA‑critical components to achieve best‑in‑class accuracy and runtime balance. Implement advanced data structures, dynamic memory management, and disk‑caching strategies to support extremely large IC designs (100M+ gates, thousands of clock domains). Drive multi‑threading enhancements and parallelization strategies for modern compute architectures. Software Infrastructure & Debugging Refactor and modernize codebases to improve maintainability, scalability, and multi‑thread performance. Build robust debugging and diagnostic infrastructure to capture detailed customer‑side failure information. Rapidly root‑cause and resolve complex timing and infrastructure issues based on limited customer feedback. Cross‑Tool Integration & EDA Ecosystem Support Develop and maintain interfaces between STA engines and synthesis, P&R, and other EDA tools. Ensure data integrity and compatibility across internal and external toolchains. Collaborate with synthesis and optimization teams to deliver cohesive end‑to‑end timing closure solutions. Customer & Product Support Support customer tape‑outs by ensuring STA robustness, accuracy, and runtime efficiency. Work with field teams to diagnose customer issues and deliver timely fixes or enhancements. Contribute to product roadmap discussions based on customer needs and industry trends. Salary Range     The pay range below is for Bay Area California only. Actual salary may vary based on   a number of   factors including job location, job-related knowledge, skills, experiences,   trainings , etc. We also offer incentive opportunities that reward employees based on individual and company performance.    $ 178.9K   - $259.0 K   USD     We use artificial intelligence to screen, assess, or select applicants for the position.   Applicants must be eligible for any required U.S. export authorizations .   Qualifications: Required Qualifications 10+ years of experience in EDA software development, with a strong focus on STA or timing‑related engines. Deep understanding of static timing analysis concepts, algorithms, and data structures. Strong C/C++ development skills and experience with large‑scale, performance‑critical codebases. Experience with multi‑threading, memory optimization, and scalable software architecture. Proven ability to debug complex issues and deliver high‑quality, production‑ready code. Preferred Qualifications Experience developing commercial STA tools or timing engines within synthesis/P&R flows. Familiarity with ASIC/FPGA design flows, clocking architectures, and timing exception handling. Background supporting customer tape‑outs or working directly with customer‑reported issues. Knowledge of disk‑caching strategies, distributed computing, or large‑design scalability techniques.​ What We Offer Opportunity to shape next‑generation STA technology used in advanced semiconductor design. A collaborative environment with deep technical expertise and complex engineering challenges. The ability to influence architecture, performance strategy, and product direction. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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