Design Verification Engineer job opportunity at Altera Corporation.

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Altera Corporation Design Verification Engineer
Experience: 12-years
Pattern: full-time
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loacation San Jose, California, United States, United States Of America
loacation San Jose, Cali..........United States Of America

Job Details: Job Description: About Altera Altera is a global leader in programmable logic solutions, delivering cutting-edge FPGA, SoC FPGA, and adaptive compute technologies that enable innovation across data centers, communications, automotive, aerospace, and industrial markets. Our culture emphasizes technical excellence, collaboration, and continuous innovation to solve the world’s most complex design challenges. Position Overview Altera is seeking a Design Verification Engineer to provide technical leadership and hands-on expertise in the verification of complex FPGA and SoC designs. This individual will play a critical role in defining verification strategies, driving methodology adoption, and ensuring the functional correctness and quality of next-generation programmable logic products. The ideal candidate is a recognized technical authority in design verification with a proven track record of delivering high-quality silicon. Key Responsibilities Serve as a technical leader for design verification efforts across complex FPGA, SoC FPGA, and IP-level designs Define, architect, and drive end-to-end verification strategies, plans, and methodologies for large-scale designs Develop and maintain advanced SystemVerilog/UVM-based verification environments, testbenches, checkers, and coverage models Collaborate closely with architecture, RTL design, firmware, and software teams from pre-architecture through post-silicon validation Lead debug and root-cause analysis of complex functional issues at block, subsystem, and full-chip levels Drive verification signoff using functional coverage, code coverage, assertions, and formal verification where applicable Mentor and technically guide senior and junior verification engineers, influencing best practices across teams Evaluate and introduce new verification technologies, tools, and methodologies to improve quality and productivity Partner with cross-functional stakeholders to ensure alignment on requirements, schedules, and quality metrics Salary Range   The pay range below is for Bay Area California only. Actual salary may vary based on   a number of   factors including job location, job-related knowledge, skills, experiences,   trainings , etc. We also offer incentive opportunities that reward employees based on individual and company performance.    $200,400 - $270,000   USD     We use artificial intelligence to screen, assess, or select applicants for the position.   Applicants must be eligible for any required U.S. export authorizations .   Qualifications: Minimum Qualifications 12+ years of hands-on Design Verification experience in FPGA, ASIC, or SoC development environments Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (Master’s or PhD preferred) Expert-level proficiency in SystemVerilog and industry-standard verification methodologies (UVM) Strong experience developing constrained-random, coverage-driven verification environments Deep understanding of digital design fundamentals, RTL design concepts, and verification signoff criteria Experience with industry-standard EDA simulation, debug, and coverage tools Proven ability to lead technically complex verification efforts and influence design and verification strategy Preferred Qualifications Experience verifying FPGA architectures, programmable logic fabrics, or high-speed IP (e.g., PCIe, Ethernet, DDR, SerDes) Hands-on experience with assertion-based verification and/or formal verification techniques Familiarity with hardware/software co-verification and embedded firmware interactions Experience supporting post-silicon validation and debug Prior experience in a technical lead or principal-level role within a semiconductor organization Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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