UVM Verification Engineer job opportunity at Celestial AI.

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Celestial AI UVM Verification Engineer
Experience: 5+years
Pattern: On Site
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Verification Engineer

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degreeBachelor's (B.Eng.)
loacation Santa Clara, California, United States Of America
loacation Santa Clara, C..........United States Of America

We are seeking an experienced Verification #Engineer with strong expertise in SystemVerilog and #UVM methodologies to join our collaborative team. You will play a key role in defining verification strategies, developing robust UVM environments, and enhancing our overall verification infrastructure. Our team works on complex IP and SoC verification, including emulation, AMS Co-Simulation, and industry-leading UVM methodologies. __ #Develop UVM testbenches, stimulus, and constraints. __ Establish detailed test plans ensuring complete functional and code coverage. __ Lead rigorous testbench reviews involving #designers, #architects, and #software engineers to uphold verification quality. __ Ensure that our SoCs are functionally correct by developing SystemVerilog/UVM verification environments. __ Create detailed verification plans for block-level, IP, and SoC-level #projects. __ Collaborate closely with ASIC and SoC #design teams to manage milestones and ensure timely deliverables. __ Drive continuous improvement of verification methodologies and processes. __ Build and optimize verification infrastructure to enhance efficiency and effectiveness. __ Coordinate with software and emulation teams to ensure first-pass tapeout success.

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